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1.发明授权Storage system having plural microprocessors, and processing allotment method for storage system having plural microprocessors 有权具有多个微处理器的存储系统以及具有多个微处理器的存储系统的处理分配方法公开(公告)号：US08694689B2
公开(公告)日：2014-04-08
申请号：US12309410
申请日：2009-01-09
申请人： Tomohiro Yoshihara , Sadahiro Sugimoto , Norio Shimozono , Noboru Morishita , Masayuki Yamamoto
发明人： Tomohiro Yoshihara , Sadahiro Sugimoto , Norio Shimozono , Noboru Morishita , Masayuki Yamamoto
CPC分类号： G06F3/0653 , G06F3/061 , G06F3/0635 , G06F3/0673 , G06F3/0683
摘要： In a storage system which includes a plurality of microprocessors, it is desired to prevent delay in I/O responses due to synchronous processing waiting for asynchronous processing, while still ensuring the throughput of asynchronous processing. In a plurality of microprocessors possessed by a controller, synchronous processors and asynchronous processors are mixed together. The synchronous processors are microprocessors whose duty is to perform synchronous processing and not to perform asynchronous processing. And the asynchronous processors are microprocessors whose duty is to perform asynchronous processing and not to perform synchronous processing.
摘要翻译： 在包括多个微处理器的存储系统中，期望防止由于等待异步处理的同步处理而导致的I / O响应延迟，同时仍然确保异步处理的吞吐量。 在由控制器拥有的多个微处理器中，将同步处理器和异步处理器混合在一起。 同步处理器是负责执行同步处理并且不执行异步处理的微处理器。 并且异步处理器是其负责执行异步处理并且不执行同步处理的微处理器。
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2.发明申请STORAGE SYSTEM HAVING PLURAL MICROPROCESSORS, AND PROCESSING ALLOTMENT METHOD FOR STORAGE SYSTEM HAVING PLURAL MICROPROCESSORS 有权具有多种微处理器的存储系统以及具有多种微处理器的存储系统的处理分配方法公开(公告)号：US20110252262A1
公开(公告)日：2011-10-13
申请号：US12309410
申请日：2009-01-09
申请人： Tomohiro Yoshihara , Sadahiro Sugimoto , Norio Shimozono , Noboru Morishita , Masayuki Yamamoto
发明人： Tomohiro Yoshihara , Sadahiro Sugimoto , Norio Shimozono , Noboru Morishita , Masayuki Yamamoto
IPC分类号： G06F1/12
CPC分类号： G06F3/0653 , G06F3/061 , G06F3/0635 , G06F3/0673 , G06F3/0683
摘要： In a storage system which includes a plurality of microprocessors, it is desired to prevent delay in I/O responses due to synchronous' processing waiting for asynchronous processing, while still ensuring the throughput of asynchronous processing. In a plurality of microprocessors possessed by a controller, synchronous processors and asynchronous processors are mixed together. The synchronous processors are microprocessors whose duty is to perform synchronous processing and not to perform asynchronous processing. And the asynchronous processors are microprocessors whose duty is to perform asynchronous processing and not to perform synchronous processing.
摘要翻译： 在包括多个微处理器的存储系统中，期望防止由于同步处理等待异步处理而导致的I / O响应延迟，同时仍然确保异步处理的吞吐量。 在由控制器拥有的多个微处理器中，将同步处理器和异步处理器混合在一起。 同步处理器是负责执行同步处理并且不执行异步处理的微处理器。 并且异步处理器是其负责执行异步处理并且不执行同步处理的微处理器。
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公开(公告)号：US09262095B2
公开(公告)日：2016-02-16
申请号：US13588226
申请日：2012-08-17
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0631 , G06F3/0658 , G06F3/0689 , G06F9/5027 , G06F12/0866 , G06F2209/509
摘要： Among a plurality of microprocessors 12, 32, when the load on a microprocessor 12 which performs I/O task processing of received I/O requests is equal to or greater than a first load, the microprocessor assigns at least an I/O task portion of the I/O task processing to another microprocessor 12 or 32, and the other microprocessor 12 or 32 executes at least the I/O task portion. The I/O task portion is a task processing portion comprising cache control processing, comprising the securing in cache memory 20 of a cache area, which is one area in cache memory 20, for storage of data.
摘要翻译： 在多个微处理器12,32中，当对接收的I / O请求执行I / O任务处理的微处理器12上的负载等于或大于第一负载时，微处理器至少分配I / O任务部分 的I / O任务处理到另一个微处理器12或32，另一个微处理器12或32至少执行I / O任务部分。 I / O任务部分是包括高速缓存控制处理的任务处理部分，包括将高速缓存区域（其是高速缓冲存储器20中的一个区域）的高速缓存存储器20固定在数据的存储中。
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公开(公告)号：US20070220514A1
公开(公告)日：2007-09-20
申请号：US11429527
申请日：2006-05-05
IPC分类号： G06F9/46
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0631 , G06F3/0658 , G06F3/0689 , G06F9/5027 , G06F12/0866 , G06F2209/509
摘要： Among a plurality of microprocessors 12, 32, when the load on a microprocessor 12 which performs I/O task processing of received I/O requests is equal to or greater than a first load, the microprocessor assigns at least an I/O task portion of the I/O task processing to another microprocessor 12 or 32, and the other microprocessor 12 or 32 executes at least the I/O task portion. The I/O task portion is a task processing portion comprising cache control processing, comprising the securing in cache memory 20 of a cache area, which is one area in cache memory 20, for storage of data.
摘要翻译： 在多个微处理器12,32中，当对接收的I / O请求执行I / O任务处理的微处理器12上的负载等于或大于第一负载时，微处理器至少分配I / O任务部分 的I / O任务处理到另一个微处理器12或32，另一个微处理器12或32至少执行I / O任务部分。 I / O任务部分是包括高速缓存控制处理的任务处理部分，其包括将高速缓存区域（其是高速缓冲存储器20中的一个区域）的高速缓存存储器20固定在数据的存储中。
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公开(公告)号：US08271979B2
公开(公告)日：2012-09-18
申请号：US11429527
申请日：2006-05-05
IPC分类号： G06F9/46
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0631 , G06F3/0658 , G06F3/0689 , G06F9/5027 , G06F12/0866 , G06F2209/509
摘要： Among a plurality of microprocessors 12, 32, when the load on a microprocessor 12 which performs I/O task processing of received I/O requests is equal to or greater than a first load, the microprocessor assigns at least an I/O task portion of the I/O task processing to another microprocessor 12 or 32, and the other microprocessor 12 or 32 executes at least the I/O task portion. The I/O task portion is a task processing portion comprising cache control processing, comprising the securing in cache memory 20 of a cache area, which is one area in cache memory 20, for storage of data.
摘要翻译： 在多个微处理器12,32中，当对接收的I / O请求执行I / O任务处理的微处理器12上的负载等于或大于第一负载时，微处理器至少分配I / O任务部分 的I / O任务处理到另一个微处理器12或32，另一个微处理器12或32至少执行I / O任务部分。 I / O任务部分是包括高速缓存控制处理的任务处理部分，其包括将高速缓存区域（其是高速缓冲存储器20中的一个区域）的高速缓存存储器20固定在数据的存储中。
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6.发明申请公开(公告)号：US20120023290A1
公开(公告)日：2012-01-26
申请号：US12738601
申请日：2010-04-05
IPC分类号： G06F12/00
CPC分类号： G06F3/0665 , G06F3/0607 , G06F3/0635 , G06F3/067 , G06F12/0866
摘要： There are a loose coupling and a tight coupling as the coupling configurations for a first module and a second module. The loose coupling is a coupling configuration in which the first and second modules are coupled together by way of a front-end path, and the first module is not able to access a second storage resource. The tight coupling is a coupling configuration in which the first and second modules are coupled together by way of a back-end path, and the first module is able to access the second storage resource. A switch from the loose coupling to the tight coupling is performed using the following processing flow without the first and second modules being partitioned into respectively independent storage modules. Specifically, first, the first and second modules are coupled together by way of the back-end path, and next, the first module merges information denoted by second management information from the second storage resource with first management information via the back-end path.
摘要翻译： 作为第一模块和第二模块的耦合配置，存在松耦合和紧耦合。 松耦合是其中第一和第二模块通过前端路径耦合在一起的耦合配置，并且第一模块不能访问第二存储资源。 紧耦合是其中第一和第二模块通过后端路径耦合在一起的耦合配置，并且第一模块能够访问第二存储资源。 使用以下处理流程，从松耦合到紧耦合的切换，而不将第一和第二模块分成独立的存储模块。 具体地说，首先，第一模块和第二模块通过后端路径耦合在一起，接下来，第一模块通过后端路径将来自第二存储资源的第二管理信息所表示的信息与第一管理信息进行合并。
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7.发明授权Storage system configured from plurality of storage modules and method for switching coupling configuration of storage modules 有权由多个存储模块配置的存储系统和用于切换存储模块的耦合配置的方法公开(公告)号：US08312234B2
公开(公告)日：2012-11-13
申请号：US12738601
申请日：2010-04-05
IPC分类号： G06F12/00
CPC分类号： G06F3/0665 , G06F3/0607 , G06F3/0635 , G06F3/067 , G06F12/0866
摘要： There are a loose coupling and a tight coupling as the coupling configurations for a first module and a second module. The loose coupling is a coupling configuration in which the first and second modules are coupled together by way of a front-end path, and the first module is not able to access a second storage resource. The tight coupling is a coupling configuration in which the first and second modules are coupled together by way of a back-end path, and the first module is able to access the second storage resource. A switch from the loose coupling to the tight coupling is performed using the following processing flow without the first and second modules being partitioned into respectively independent storage modules. Specifically, first, the first and second modules are coupled together by way of the back-end path, and next, the first module merges information denoted by second management information from the second storage resource with first management information via the back-end path.
摘要翻译： 作为第一模块和第二模块的耦合配置，存在松耦合和紧耦合。 松耦合是其中第一和第二模块通过前端路径耦合在一起的耦合配置，并且第一模块不能访问第二存储资源。 紧耦合是其中第一和第二模块通过后端路径耦合在一起的耦合配置，并且第一模块能够访问第二存储资源。 使用以下处理流程，从松耦合到紧耦合的切换，而不将第一和第二模块分成独立的存储模块。 具体地说，首先，第一模块和第二模块通过后端路径耦合在一起，接下来，第一模块通过后端路径将来自第二存储资源的第二管理信息所表示的信息与第一管理信息进行合并。
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公开(公告)号：US20110246701A1
公开(公告)日：2011-10-06
申请号：US12527441
申请日：2009-03-24
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7208 , G06F2212/7211 , G11C16/349 , G11C16/3495
摘要： Efficient leveling among a plurality of FMPKs 130 including a newly added or replaced FMPK 130. When a storage controller 110 lacks free blocks in real FMPKs 130 and any FMPK 130 of the real FMPKs 130 and an added substitute FMPK 130 are selected as leveling object devices, if the attribute of a block in the real FMPK 130 belonging to the leveling object devices is “Hot,” data larger than a threshold value from among data belonging to that block is migrated to a block in the substitute FMPK 130; or if the attribute of a block in the real FMPK 130 belonging to the leveling object devices is “Cold,” data smaller than the threshold value from among data belonging to that block is migrated to a block in the substitute FMPK 130.
摘要翻译： 包括新添加或替换的FMPK 130的多个FMPK 130中的高效调平。当存储控制器110在实际FMPK 130中缺少空闲块并且真实FMPK 130的任何FMPK 130和添加的替换FMPK 130被选择为调平对象设备 如果属于调平对象设备的实际FMPK 130中的块的属性为“Hot”，则属于该块的数据中大于阈值的数据被迁移到替代FMPK 130中的块; 或者如果属于调平对象装置的真实FMPK 130中的块的属性为“冷”，则属于该块的数据中小于阈值的数据被迁移到替代FMPK 130中的块。
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公开(公告)号：US20110191547A1
公开(公告)日：2011-08-04
申请号：US12665080
申请日：2009-11-19
IPC分类号： G06F12/00
CPC分类号： G06F3/0631 , G06F3/0605 , G06F3/0613 , G06F3/067
摘要： A computer system having a plurality of controllers for data input/output control is provided, wherein even if a control authority of a processor is transferred to another processor and the computer system migrates control information necessary for a controller to execute data input/output processing, from a shared memory to a local memory for the relevant controller, the computer system prevents the occurrence of unbalanced allocation of a control function necessary for data input/output control between the plurality of controllers; and a load equalization method for such a computer system is also provided.
摘要翻译： 提供一种具有用于数据输入/输出控制的多个控制器的计算机系统，其中即使处理器的控制权限被传送到另一处理器，并且计算机系统迁移控制器执行数据输入/输出处理所需的控制信息， 从共享存储器到相关控制器的本地存储器，计算机系统防止在多个控制器之间数据输入/输出控制所需的控制功能的不平衡分配的发生; 并且还提供了一种用于这种计算机系统的负载均衡方法。
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10.发明授权Computer system and load equalization control method for the same where cache memory is allocated to controllers 有权同样的计算机系统和负载均衡控制方法，其中缓存存储器被分配给控制器公开(公告)号：US08341348B2
公开(公告)日：2012-12-25
申请号：US12665080
申请日：2009-11-19
IPC分类号： G06F13/00
CPC分类号： G06F3/0631 , G06F3/0605 , G06F3/0613 , G06F3/067
摘要： A computer system having a plurality of controllers for data input/output control is provided, wherein even if a control authority of a processor is transferred to another processor and the computer system migrates control information necessary for a controller to execute data input/output processing, from a shared memory to a local memory for the relevant controller, the computer system prevents the occurrence of unbalanced allocation of a control function necessary for data input/output control between the plurality of controllers; and a load equalization method for such a computer system is also provided.
摘要翻译： 提供一种具有用于数据输入/输出控制的多个控制器的计算机系统，其中即使处理器的控制权限被传送到另一处理器，并且计算机系统迁移控制器执行数据输入/输出处理所需的控制信息， 从共享存储器到相关控制器的本地存储器，计算机系统防止在多个控制器之间数据输入/输出控制所需的控制功能的不平衡分配的发生; 并且还提供了一种用于这种计算机系统的负载均衡方法。
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