公开(公告)号：US08700856B2

公开(公告)日：2014-04-15

申请号：US13501022

申请日：2012-03-23

申请人： Katsuya Tanaka ,  Masanori Takada ,  Shintaro Kudo

发明人： Katsuya Tanaka ,  Masanori Takada ,  Shintaro Kudo

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F3/06

CPC分类号： G06F12/0808 ,  G06F3/0646 ,  G06F11/1666 ,  G06F11/2017 ,  H04L49/552

摘要： According to a prior art storage subsystem, shared memories are mirrored in main memories of two processors providing redundancy. When the consistency of writing order of data is not ensured among mirrored shared memories, the processors must read only one of the mirrored shared memories to have the write order of the read data correspond among the two processors. As a result, upon reading data from the shared memories, it is necessary for a processor to read data from the main memory of the other processor, so that the overhead is increased compared to the case where the respective processors read their respective main memories. According to the storage subsystem of the present invention, a packet redirector having applied a non-transparent bridge enables to adopt a PCI Express multicast to the writing of data from the processor to the main memory, so that the order of writing data into the shared memories can be made consistent among the mirrored memories. As a result, data can be read from the shared memories speedily by accessing respective main memories in the respective processors.

摘要翻译： 根据现有技术的存储子系统，共享存储器被镜像在提供冗余的两个处理器的主存储器中。 当在镜像共享存储器中不能确保数据的写入次序的一致性时，处理器必须只读取一个镜像的共享存储器，以使两个处理器之间的读取数据的写入顺序相对应。 结果，在从共享存储器读取数据时，处理器需要从另一个处理器的主存储器读取数据，从而与相应的处理器读取它们各自的主存储器的情况相比，增加了开销。 根据本发明的存储子系统，应用非透明桥的分组重定向器使得能够采用PCI Express组播来从处理器向主存储器写入数据，从而将数据写入共享的顺序 记忆可以在镜像记忆中保持一致。 结果，可以通过访问相应处理器中的相应主存储器来快速地从共享存储器读取数据。

公开(公告)号：US5808814A

公开(公告)日：1998-09-15

申请号：US683288

申请日：1996-07-18

申请人： Shintaro Kudo

发明人： Shintaro Kudo

IPC分类号： G02B11/28 ,  G02B13/14 ,  G02B13/24 ,  G03F7/20 ,  H01L21/027 ,  G02B9/00 ,  G02B9/60

CPC分类号： G03F7/70241 ,  G02B13/14 ,  G02B13/24 ,  G03F7/7025

摘要： A short wavelength reduction projection optical system used for transferring integrated circuit patterns from a reticle to a wafer in a semiconductor manufacturing system. The optical system has object side and image side virtually telecentric, high resolution over a wide exposure area, and adequately compensates for optical aberrations without increasing the length of the optical system. The optical system has a first group of lenses with weak refractive power, a second group of lenses with a positive refractive power, a third group of lenses with a negative refractive power, a fourth group of lenses with a positive refractive power, and an aperture stop located between the third and fourth groups of lenses.

摘要翻译： 一种用于在半导体制造系统中将集成电路图案从掩模版传送到晶片的短波长减小投影光学系统。 光学系统具有物体侧和像侧在宽曝光区域上实质上远心，高分辨率，并且在不增加光学系统的长度的情况下充分地补偿光学像差。 光学系统具有第一组屈光力弱的透镜，具有正屈光力的第二组透镜，具有负屈光力的第三组透镜，具有正屈光力的第四组透镜，以及孔径 位于第三组和第四组透镜之间。

公开(公告)号：US08713577B2

公开(公告)日：2014-04-29

申请号：US13140622

申请日：2011-06-03

申请人： Shintaro Kudo ,  Norio Shimozono ,  Akira Deguchi

发明人： Shintaro Kudo ,  Norio Shimozono ,  Akira Deguchi

IPC分类号： G06F9/46

CPC分类号： G06F3/0635 ,  G06F3/0611 ,  G06F3/0685

摘要： The storage apparatus includes a plurality of microprocessors; a plurality of storage areas formed in a drive group configured from a plurality of physical drives; and a management unit which manages microprocessors which handle data I/Os to/from one or more storage areas among the plurality of storage areas. The management unit detects variations in the processing loads of the plurality of microprocessors, generates load balancing target information which includes information on the storage areas to which the ownership is migrated, information on the migration-source microprocessor serving as the migration source of the ownership, and information on the migration-destination microprocessor serving as the migration destination of the ownership, and migrates the ownership to the storage areas with timing such that there is no drop in the processing load of the migration-destination microprocessor contained in the load balancing target information.

摘要翻译： 存储装置包括多个微处理器; 形成在由多个物理驱动器构成的驱动组中的多个存储区域; 以及管理单元，其管理对所述多个存储区域中的一个或多个存储区域处理数据I / O的微处理器。 管理单元检测多个微处理器的处理负荷的变化，生成负载平衡目标信息，其包括关于所有权迁移的存储区域的信息，关于作为所有权的迁移源的迁移源微处理器的信息， 以及关于作为所有权的迁移目的地的迁移目的地微处理器的信息，并且将所有权迁移到存储区域，使得包含在负载均衡目标信息中的迁移目的地微处理器的处理负荷不会下降 。

公开(公告)号：US08650576B2

公开(公告)日：2014-02-11

申请号：US13140300

申请日：2011-06-03

申请人： Akira Deguchi ,  Shintaro Kudo

发明人： Akira Deguchi ,  Shintaro Kudo

IPC分类号： G06F9/46

CPC分类号： G06F3/0635 ,  G06F3/061 ,  G06F3/0689 ,  G06F2206/1012

摘要： The overall processing function of a storage apparatus is improved by suitably migrating ownership.The storage apparatus comprises a plurality of microprocessors; a plurality of storage areas formed in a drive group configured from a plurality of physical drives; and a management unit which manages, as the microprocessors which possess ownership to the storage areas, the microprocessors which handle data I/Os to/from one or more storage areas among the plurality of storage areas, wherein the management unit detects variations in the processing loads of the plurality of microprocessors, selects a migration-source microprocessor which migrates the ownership and a migration-destination microprocessor which is the ownership migration destination on the basis of variations in the processing load, and determines whether to migrate the ownership on the basis of information on a usage status of resources of each of the storage areas to which the migration-source microprocessor possesses ownership.

摘要翻译： 通过适当地迁移所有权来改善存储装置的整体处理功能。 存储装置包括多个微处理器; 形成在由多个物理驱动器构成的驱动组中的多个存储区域; 以及管理单元，其管理对所述存储区域拥有所有权的微处理器，所述微处理器处理与所述多个存储区域中的一个或多个存储区域之间的数据I / O，其中所述管理单元检测所述处理中的变化 多个微处理器的负载，基于处理负载的变化，选择迁移所有权的迁移源微处理器和作为所有权迁移目的地的迁移目的地微处理器，并且基于 关于迁移源微处理器拥有所有权的每个存储区域的资源的使用状态的信息。

公开(公告)号：US09021214B2

公开(公告)日：2015-04-28

申请号：US13380218

申请日：2011-12-14

申请人： Yuki Sakashita ,  Shintaro Kudo ,  Yusuke Nonaka

发明人： Yuki Sakashita ,  Shintaro Kudo ,  Yusuke Nonaka

IPC分类号： G06F12/00 ,  G06F3/06

CPC分类号： G06F3/0658 ,  G06F3/061 ,  G06F3/0626 ,  G06F3/067 ,  G06F3/0689

摘要： According to a storage system of a prior art adopting a cluster structure, various types of large-capacity memories were arranged to enhance the access performance, so that the system required a dedicated control circuit, and there was difficulty in realizing cost reduction and improvement of access performance simultaneously. In order to solve the problems, the present invention provides a storage system in which a group of memories is integrated to MPU memories directly coupled to MPUs in respective controller units, wherein each MPU memory is divided into a duplication information area and a non-duplication information area, and attribute information for controlling accesses thereto are provided. Further, each duplication information area is provided with a double master information area capable of referring to a first memory and a second memory and a single master information area capable of referring only to either the first memory or the second memory, and the accesses thereto are performed based on the attribute information.

摘要翻译： 根据采用集群结构的现有技术的存储系统，布置了各种类型的大容量存储器以增强访问性能，使得系统需要专用控制电路，并且难以实现成本降低和改进 访问性能同时进行。 为了解决这些问题，本发明提供一种存储系统，其中一组存储器集成到相应控制器单元中直接耦合到MPU的MPU存储器中，其中每个MPU存储器被分为复制信息区域和不重复的 信息区域和用于控制其访问的属性信息。 此外，每个复制信息区域都设置有能够参考第一存储器和第二存储器的双重主信息区域以及仅能够参考第一存储器或第二存储器的单个主信息区域，并且访问它们 基于属性信息执行。

公开(公告)号：US09003081B2

公开(公告)日：2015-04-07

申请号：US13512833

申请日：2012-05-18

申请人： Shintaro Kudo ,  Yusuke Nonaka

发明人： Shintaro Kudo ,  Yusuke Nonaka

IPC分类号： G06F3/00 ,  G06F5/00 ,  G06F3/06

CPC分类号： G06F13/34 ,  G06F3/0611 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/067 ,  G06F13/1642

摘要： The present invention is a clustered storage system with which, even when access to the processor of another controller is sent from the processor of one controller, the processor of the second controller is able to prioritize processing of this access so that I/O processing is also prevented from being delayed. With the storage system of the present invention, the first processor of the first controller transmits request information which is to be processed by the second processor of the second controller to the second processor by differentiating between request information for which processing is to be prioritized by the second processor and request information for which processing is not to be prioritized, and the second processor acquires the request information by differentiating between request information for which processing is to be prioritized and request information for which processing is not to be prioritized.

摘要翻译： 本发明是一种集群存储系统，即使当从一个控制器的处理器发送对另一控制器的处理器的访问时，第二控制器的处理器能够对该访问的处理进行优先级处理，以便I / O处理是 也阻止了延迟。 利用本发明的存储系统，第一控制器的第一处理器通过区分由第二控制器的第二处理器处理的请求信息来区分待优先处理的请求信息， 第二处理器和处理不优先的请求信息，并且第二处理器通过区分要优先处理的请求信息和不优先处理的请求信息来获取请求信息。

公开(公告)号：US20140108727A1

公开(公告)日：2014-04-17

申请号：US13643440

申请日：2012-10-11

申请人： YUKI Sakashita ,  Yusuke Nonaka ,  Shintaro Kudo

发明人： YUKI Sakashita ,  Yusuke Nonaka ,  Shintaro Kudo

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F3/061 ,  G06F3/065 ,  G06F3/0689 ,  G06F12/0802 ,  G06F12/0866 ,  G06F12/0888 ,  G06F12/126 ,  G06F2212/601

摘要： To raise the CPU cache hit rate and improve the I/O processing. Controller is CPU configured from a CPU core and a CPU cache wherein the CPU selects memory bus optimization execution processing or cache poisoning optimization execution processing according to an attribute of the access target volume on the basis of an access request. If the memory bus optimization execution processing is selected, CPU loads the target data into the CPU core after storing the target data in the main storage area, and if the cache poisoning optimization execution processing is selected, the CPU loads the target data into the CPU core after storing the target data in the temporary area of the CPU cache from the CPU memory, and the CPU core checks the target data which was loaded from the main storage area or the temporary area of the CPU cache.

摘要翻译： 提高CPU缓存命中率，改善I / O处理。 控制器是由CPU核心和CPU高速缓存组成的CPU，其中CPU基于访问请求，根据访问目标卷的属性来选择存储器总线优化执行处理或高速缓存中毒优化执行处理。 如果选择了存储器总线优化执行处理，则CPU将目标数据存储在主存储区域之后，将目标数据加载到CPU内核中，并且如果选择了高速缓存中毒优化执行处理，则CPU将目标数据加载到CPU 将目标数据从CPU存储器存储在CPU高速缓存的临时区域中，并且CPU核心检查从主存储区域或CPU高速缓存的临时区域加载的目标数据。

公开(公告)号：US20130311685A1

公开(公告)日：2013-11-21

申请号：US13512833

申请日：2012-05-18

申请人： Shintaro Kudo ,  Yusuke Nonaka

发明人： Shintaro Kudo ,  Yusuke Nonaka

IPC分类号： G06F3/00

CPC分类号： G06F13/34 ,  G06F3/0611 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/067 ,  G06F13/1642

摘要： The present invention is a clustered storage system with which, even when access to the processor of another controller is sent from the processor of one controller, the processor of the second controller is able to prioritize processing of this access so that I/O processing is also prevented from being delayed. With the storage system of the present invention, the first processor of the first controller transmits request information which is to be processed by the second processor of the second controller to the second processor by differentiating between request information for which processing is to be prioritized by the second processor and request information for which processing is not to be prioritized, and the second processor acquires the request information by differentiating between request information for which processing is to be prioritized and request information for which processing is not to be prioritized.

公开(公告)号：US20130159620A1

公开(公告)日：2013-06-20

申请号：US13380218

申请日：2011-12-14

申请人： Yuki Sakashita ,  Shintaro Kudo ,  Yusuke Nonaka

发明人： Yuki Sakashita ,  Shintaro Kudo ,  Yusuke Nonaka

IPC分类号： G06F12/08 ,  G06F12/16

CPC分类号： G06F3/0658 ,  G06F3/061 ,  G06F3/0626 ,  G06F3/067 ,  G06F3/0689

摘要： According to a storage system of a prior art adopting a cluster structure, various types of large-capacity memories were arranged to enhance the access performance, so that the system required a dedicated control circuit, and there was difficulty in realizing cost reduction and improvement of access performance simultaneously. In order to solve the problems, the present invention provides a storage system in which a group of memories is integrated to MPU memories directly coupled to MPUs in respective controller units, wherein each MPU memory is divided into a duplication information area and a non-duplication information area, and attribute information for controlling accesses thereto are provided. Further, each duplication information area is provided with a double master information area capable of referring to a first memory and a second memory and a single master information area capable of referring only to either the first memory or the second memory, and the accesses thereto are performed based on the attribute information.

摘要翻译： 根据采用集群结构的现有技术的存储系统，布置了各种类型的大容量存储器以增强访问性能，使得系统需要专用控制电路，并且难以实现成本降低和改进 访问性能同时进行。 为了解决这些问题，本发明提供一种存储系统，其中一组存储器集成到相应控制器单元中直接耦合到MPU的MPU存储器中，其中每个MPU存储器被分为复制信息区域和不重复的 信息区域和用于控制其访问的属性信息。 此外，每个复制信息区域都设置有能够参考第一存储器和第二存储器的双重主信息区域以及仅能够参考第一存储器或第二存储器的单个主信息区域，并且访问它们 基于属性信息执行。

公开(公告)号：US20120311603A1

公开(公告)日：2012-12-06

申请号：US13140622

申请日：2011-06-03

申请人： Shintaro Kudo ,  Norio Shimozono ,  Akira Deguchi

发明人： Shintaro Kudo ,  Norio Shimozono ,  Akira Deguchi

IPC分类号： G06F9/46

CPC分类号： G06F3/0635 ,  G06F3/0611 ,  G06F3/0685

摘要： The overall processing performance of a storage apparatus is improved by migrating MPPK ownership with suitable timing.The storage apparatus comprises a plurality of microprocessors; a plurality of storage areas formed in a drive group configured from a plurality of physical drives; and a management unit which manages, as the microprocessors which possess ownership to the storage areas, the microprocessors which handle data I/Os to/from one or more storage areas among the plurality of storage areas, wherein the management unit detects variations in the processing loads of the plurality of microprocessors, generates, on the basis of variations in the processing load, load balancing target information which includes information on the storage areas to which the ownership is migrated, information on the migration-source microprocessor serving as the migration source of the ownership, and information on the migration-destination microprocessor serving as the migration destination of the ownership, and migrates the ownership to the storage areas with timing such that there is no drop in the processing load of the migration-destination microprocessor contained in the load balancing target information.

摘要翻译： 通过以适当的时机迁移MPPK所有权，可以提高存储设备的整体处理性能。 存储装置包括多个微处理器; 形成在由多个物理驱动器构成的驱动组中的多个存储区域; 以及管理单元，其管理对所述存储区域拥有所有权的微处理器，所述微处理器处理与所述多个存储区域中的一个或多个存储区域对应的数据I / O，其中所述管理单元检测所述处理中的变化 多个微处理器的负载基于处理负载的变化生成包括关于所有权迁移的存储区域的信息的负载均衡目标信息，作为迁移源的迁移源微处理器的信息 所有权和关于作为所有权的迁移目的地的迁移目的地微处理器的信息，并且将所有权迁移到存储区域，其时间使得包含在负载中的迁移目的地微处理器的处理负载不会下降 平衡目标信息。