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公开(公告)号：US08555224B2
公开(公告)日：2013-10-08
申请号：US13471061
申请日：2012-05-14
申请人： Tomoyuki Ishizu , Kyouji Yamashita , Gaku Suzuki
发明人： Tomoyuki Ishizu , Kyouji Yamashita , Gaku Suzuki
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , G06F17/5036
摘要： The present disclosure provides a method of performing circuit simulation of electrical characteristics of a transistor formed on a semiconductor substrate using calculators, each of which includes a memory. A first calculator receives mask layout data and distance-dependent data indicating a distance from the target transistor. Then, a second calculator calculates an area ratio of a layout pattern of a predetermined mask from the received mask layout data, and calculates a parameter α based on the area ratio and the distance-dependent data. Then, the second calculator B calculates a change ΔP in the electrical characteristics of the transistor based on the parameter α. This configuration provides highly accurate circuit simulation of the electrical characteristics of the transistor, which depend on variations in temperature distribution of the semiconductor substrate during heat treatment due to the mask layout pattern around the transistor.
摘要翻译： 本公开提供了一种使用计算器来执行形成在半导体衬底上的晶体管的电特性的电路仿真的方法，每个都包括存储器。 第一计算器接收掩模布局数据和指示距离目标晶体管的距离的距离相关数据。 然后，第二计算器从接收到的掩模布局数据计算预定掩模的布局图案的面积比，并且基于面积比和距离相关数据计算参数α。 然后，第二计算器B基于参数α计算晶体管的电特性中的变化ΔP。 该配置提供了晶体管的电特性的高度精确的电路仿真，其取决于由于晶体管周围的掩模布局图案而在热处理期间半导体衬底的温度分布的变化。
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公开(公告)号：US20080077378A1
公开(公告)日：2008-03-27
申请号：US11822781
申请日：2007-07-10
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F17/5022
摘要： A circuit simulation apparatus has a means to acquire data regarding a transistor, a model parameter generation unit for generating a model parameter representing effects of stress upon the transistor active region caused by the isolation region, and a simulation execution unit for evaluating characteristics of the transistor using a simulation program associated with the model parameter. The model parameter includes a term regarding width of the transistor active region, a term regarding width of the peripheral active region, and a term regarding width between the transistor active region and the peripheral active region.
摘要翻译： 电路模拟装置具有获取关于晶体管的数据的模块，用于产生表示由隔离区域引起的晶体管有源区上的应力的影响的模型参数的模型参数生成单元，以及用于评估晶体管的特性的模拟执行单元 使用与模型参数相关联的模拟程序。 模型参数包括关于晶体管有源区的宽度的术语，关于外围有源区的宽度的术语，以及关于晶体管有源区和外围有源区之间的宽度的项。
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公开(公告)号：US20080027700A1
公开(公告)日：2008-01-31
申请号：US11878196
申请日：2007-07-23
申请人： Akinari Kinoshita , Tomoyuki Ishizu
发明人： Akinari Kinoshita , Tomoyuki Ishizu
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A simulation model of BT instability of a transistor in a semiconductor integrated circuit, wherein a bias condition of at least one terminal among the drain terminal, the source terminal and the substrate terminal of the transistor is set up as an independent bias condition from other terminals; and then a model parameter of the transistor is changed in the set bias condition.
摘要翻译： 半导体集成电路中的晶体管的BT不稳定性的模拟模型，其中，晶体管的漏极端子，源极端子和衬底端子中的至少一个端子的偏置条件被设置为与其它端子的独立偏置条件 ; 然后在设定偏置条件下改变晶体管的模型参数。
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公开(公告)号：US08271254B2
公开(公告)日：2012-09-18
申请号：US11878196
申请日：2007-07-23
申请人： Akinari Kinoshita , Tomoyuki Ishizu
发明人： Akinari Kinoshita , Tomoyuki Ishizu
CPC分类号： G06F17/5036
摘要： A simulation model of BT instability of a transistor in a semiconductor integrated circuit, wherein a bias condition of at least one terminal among the drain terminal, the source terminal and the substrate terminal of the transistor is set up as an independent bias condition from other terminals; and then a model parameter of the transistor is changed in the set bias condition.
摘要翻译： 半导体集成电路中的晶体管的BT不稳定性的模拟模型，其中，晶体管的漏极端子，源极端子和衬底端子中的至少一个端子的偏置条件被设置为与其它端子的独立偏置条件 ; 然后在设定偏置条件下改变晶体管的模型参数。
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公开(公告)号：US20070221962A1
公开(公告)日：2007-09-27
申请号：US11653326
申请日：2007-01-16
申请人： Tomoyuki Ishizu
发明人： Tomoyuki Ishizu
IPC分类号： H01L27/148
CPC分类号： H01L29/045 , H01L29/7843
摘要： An active region and an isolation region are formed in the surface of a silicon semiconductor substrate having a (100) crystal plane as a principal surface. A gate insulating film and a gate electrode are formed on the active region in this order. A stress control film is formed to cover part of the active region where the gate electrode is not formed, the isolation region, the top surface of the gate electrode and sidewalls. A pair of stress control regions are formed to sandwich the gate electrode in the gate width direction of the gate electrode. In the stress control regions, the stress control film is not formed, or alternatively, a stress control film thinner than the stress control film formed on the gate electrode is formed.
摘要翻译： 在具有（100）晶面作为主表面的硅半导体衬底的表面中形成有源区和隔离区。 依次在有源区上形成栅极绝缘膜和栅电极。 形成应力控制膜以覆盖未形成栅电极的有源区的一部分，隔离区，栅电极的顶表面和侧壁。 形成一对应力控制区，以在栅电极的栅极宽度方向上夹着栅电极。 在应力控制区域中，不形成应力控制膜，或者替代地，形成比形成在栅电极上的应力控制膜更薄的应力控制膜。
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6.发明授权Semiconductor device and method for manufacturing the same for improving the performance of mis transistors 有权半导体装置及其制造方法，用于改善误晶体管的性能公开(公告)号：US07964899B2
公开(公告)日：2011-06-21
申请号：US11653326
申请日：2007-01-16
申请人： Tomoyuki Ishizu
发明人： Tomoyuki Ishizu
IPC分类号： H01L27/148 , H01L29/04
CPC分类号： H01L29/045 , H01L29/7843
摘要： An active region and an isolation region are formed in the surface of a silicon semiconductor substrate having a (100) crystal plane as a principal surface. A gate insulating film and a gate electrode are formed on the active region in this order. A stress control film is formed to cover part of the active region where the gate electrode is not formed, the isolation region, the top surface of the gate electrode and sidewalls. A pair of stress control regions are formed to sandwich the gate electrode in the gate width direction of the gate electrode. In the stress control regions, the stress control film is not formed, or alternatively, a stress control film thinner than the stress control film formed on the gate electrode is formed.
摘要翻译： 在具有（100）晶面作为主表面的硅半导体衬底的表面中形成有源区和隔离区。 依次在有源区上形成栅极绝缘膜和栅电极。 形成应力控制膜以覆盖未形成栅电极的有源区的一部分，隔离区，栅电极的顶表面和侧壁。 形成一对应力控制区，以在栅电极的栅极宽度方向上夹着栅电极。 在应力控制区域中，不形成应力控制膜，或者替代地，形成比形成在栅电极上的应力控制膜更薄的应力控制膜。
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公开(公告)号：US07792663B2
公开(公告)日：2010-09-07
申请号：US11822781
申请日：2007-07-10
IPC分类号： G06F17/10
CPC分类号： G06F17/504 , G06F17/5022
摘要： A circuit simulation apparatus has a means to acquire data regarding a transistor, a model parameter generation unit for generating a model parameter representing effects of stress upon the transistor active region caused by the isolation region, and a simulation execution unit for evaluating characteristics of the transistor using a simulation program associated with the model parameter. The model parameter includes a term regarding width of the transistor active region, a term regarding width of the peripheral active region, and a term regarding width between the transistor active region and the peripheral active region.
摘要翻译： 电路模拟装置具有获取关于晶体管的数据的模块，用于产生表示由隔离区域引起的晶体管有源区上的应力的影响的模型参数的模型参数生成单元，以及用于评估晶体管的特性的模拟执行单元 使用与模型参数相关联的模拟程序。 模型参数包括关于晶体管有源区的宽度的术语，关于外围有源区的宽度的术语，以及关于晶体管有源区和外围有源区之间的宽度的项。
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8.发明授权Semiconductor device layout reducing imbalance characteristics of paired transistors 有权半导体器件布局减少成对晶体管的不平衡特性公开(公告)号：US08575703B2
公开(公告)日：2013-11-05
申请号：US13034160
申请日：2011-02-24
申请人： Tomoyuki Ishizu
发明人： Tomoyuki Ishizu
IPC分类号： H01L21/70
CPC分类号： H01L27/088 , H01L21/823807 , H01L27/0207 , H01L27/092 , H01L27/11 , H01L27/1104 , H01L29/6659
摘要： In a semiconductor device having paired transistors, an imbalance in characteristics of the paired transistors is reduced or prevented while an increase in circuit area is reduced or prevented. First and second transistors have first and second regions having the same active region pattern, and third and fourth transistors have third and fourth regions having the same active region pattern. The active regions of the third and fourth transistors have a longer length in the channel length direction than that of the active regions of the first and second transistors. The third and fourth regions have a narrower width in the channel length direction than that of the first and second regions.
摘要翻译： 在具有成对晶体管的半导体器件中，减少或防止成对晶体管的特性不平衡，同时降低或防止电路面积的增加。 第一和第二晶体管具有第一和第二区域具有相同的有源区域图案，并且第三和第四晶体管具有相同的有源区域图案的第三和第四区域。 第三和第四晶体管的有源区在沟道长度方向的长度比第一和第二晶体管的有源区的长度长。 第三区域和第四区域的沟道长度方向上的宽度比第一区域和第二区域宽。
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公开(公告)号：US20060142987A1
公开(公告)日：2006-06-29
申请号：US11313994
申请日：2005-12-22
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A circuit simulation apparatus and a modeling method are provided which are useful to design an integrated circuit in a very fine manner by forming a model of such a transistor that widths of element isolating-purpose insulating films are different from each other. In an isolation width depending parameter correcting means 4 of the present invention, an approximate expression of a parameter having an element isolating-purpose insulating film width depending characteristic is formed, and a value of a corrected parameter obtained by employing the formed approximate expression is replaced by a value of an original parameter, so that a transistor model of such a transistor is formed in which element isolating-purpose insulating film widths are different from each other. As a consequence, circuit simulation can be carried out in high precision by considering a change in transistor characteristics caused by a stress, which are approximated to actually measured data.
摘要翻译： 提供了一种电路模拟装置和建模方法，其通过形成元件隔离用绝缘膜的宽度彼此不同的这种晶体管的模型，以非常精细的方式设计集成电路是有用的。 在本发明的隔离宽度相关参数校正装置4中，形成具有元件隔离用绝缘膜宽度依赖特性的参数的近似表达式，并且替换通过使用形成的近似表达式而获得的校正参数的值 通过原始参数的值，使得形成这种晶体管的晶体管模型，其中元件隔离用绝缘膜宽度彼此不同。 因此，可以通过考虑由近似于实际测量数据的应力引起的晶体管特性的变化，可以高精度地进行电路仿真。
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