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公开(公告)号：US07476957B2
公开(公告)日：2009-01-13
申请号：US11979669
申请日：2007-11-07
IPC分类号： H01L21/26
CPC分类号： H01L27/0207 , H01L21/82385 , H01L21/823892 , H01L27/0922
摘要： An integrated circuit includes: a first well of a first conductivity type; a second well of a second conductivity type coming into contact with the first well at a well boundary extending in a gate length direction; a first transistor having a first active region of the second conductivity type provided in the first well; and a second transistor which has a second active region of the second conductivity type provided in the first well and differing from the first active region in length in a gate width direction. The center location of the first active region in the gate width direction is aligned with the center location of the second active region in the gate width direction with reference to the well boundary.
摘要翻译： 集成电路包括：第一导电类型的第一阱; 第二导电类型的第二阱在沿栅极长度方向延伸的阱边界处与第一阱接触; 第一晶体管，具有设置在第一阱中的第二导电类型的第一有源区; 以及第二晶体管，其具有设置在第一阱中的第二导电类型的第二有源区，并且与栅极宽度方向上的第一有源区的长度不同。 第一有源区域在栅极宽度方向上的中心位置与第二有源区域相对于阱边界在栅极宽度方向上的中心位置对准。
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公开(公告)号：US20080142898A1
公开(公告)日：2008-06-19
申请号：US11979669
申请日：2007-11-07
IPC分类号： H01L27/092
CPC分类号： H01L27/0207 , H01L21/82385 , H01L21/823892 , H01L27/0922
摘要： An integrated circuit includes: a first well of a first conductivity type; a second well of a second conductivity type coming into contact with the first well at a well boundary extending in a gate length direction; a first transistor having a first active region of the second conductivity type provided in the first well; and a second transistor which has a second active region of the second conductivity type provided in the first well and differing from the first active region in length in a gate width direction. The center location of the first active region in the gate width direction is aligned with the center location of the second active region in the gate width direction with reference to the well boundary.
摘要翻译： 集成电路包括：第一导电类型的第一阱; 第二导电类型的第二阱在沿栅极长度方向延伸的阱边界处与第一阱接触; 第一晶体管，具有设置在第一阱中的第二导电类型的第一有源区; 以及第二晶体管，其具有设置在第一阱中的第二导电类型的第二有源区，并且与栅极宽度方向上的第一有源区的长度不同。 第一有源区域在栅极宽度方向上的中心位置与第二有源区域相对于阱边界在栅极宽度方向上的中心位置对准。
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公开(公告)号：US20080042214A1
公开(公告)日：2008-02-21
申请号：US11892053
申请日：2007-08-20
IPC分类号： H01L27/092 , H01L29/78
CPC分类号： H01L21/76895 , H01L21/823475 , H01L27/0207
摘要： A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.
摘要翻译： 半导体器件包括半导体衬底; 扩散区，其形成在半导体衬底中并用作用于形成MIS晶体管的区域; 围绕扩散区域的元件隔离区域; 形成在扩散区域和元件隔离区域两侧的至少一个栅极导体膜包括位于扩散区域上的栅极电极部分和位于元件隔离区域上的栅极互连部件，并且栅极长度具有恒定的尺寸 方向; 以及覆盖所述栅电极的层间绝缘膜。 半导体器件还包括通过层间绝缘膜的栅极接触，连接到栅极互连部分，并且具有大于栅极互连部分的栅极长度方向的尺寸。
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公开(公告)号：US20060282249A1
公开(公告)日：2006-12-14
申请号：US11349077
申请日：2006-02-08
申请人： Daisaku Ikoma , Kyoji Yamashita , Katsuhiro Ootani
发明人： Daisaku Ikoma , Kyoji Yamashita , Katsuhiro Ootani
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In designing a semiconductor integrated circuit, circuit information used for circuit simulation is extracted from measurement values of electric characteristics of a device included in TEG and parameters included in a netlist are modified using the measurement values and simulation values. Circuit simulation is carried out using the thus modified netlist to lead to a decrease in error in the circuit simulation which is caused due to difference between design dimension and actual finished dimension, thereby preventing an increase in design margin and a yield lowering by malfunction.
摘要翻译： 在设计半导体集成电路时，从包含在TEG中的设备的电特性的测量值中提取用于电路仿真的电路信息，并且使用测量值和模拟值来修改网表中包括的参数。 使用如此修改的网表进行电路仿真，导致由于设计尺寸和实际成品尺寸之间的差异导致的电路仿真中的误差减小，从而防止设计裕度增加和故障产生降低。
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公开(公告)号：US08013361B2
公开(公告)日：2011-09-06
申请号：US11270602
申请日：2005-11-10
申请人： Kyoji Yamashita , Katsuhiro Otani , Katsuya Arai , Daisaku Ikoma
发明人： Kyoji Yamashita , Katsuhiro Otani , Katsuya Arai , Daisaku Ikoma
IPC分类号： H01L27/118
CPC分类号： H01L29/78 , H01L21/76895 , H01L21/823425 , H01L21/823475 , H01L27/11807 , H01L29/4238
摘要： Gate electrodes 5A through 5F are formed to have the same geometry, and protruding parts of the gate electrodes 5A through 5F extend across an isolation region onto impurity diffusion regions. The gate electrode 5B and P-type impurity diffusion regions 7B6 are connected through a shared contact 9A1 to a first-level interconnect M1H, and the gate electrode 5E and N-type impurity diffusion regions 7A6 are connected through a shared contact 9A2 to a first-level interconnect M1I. In this way, contact pad parts of the gate electrodes 5A through 5F can be located apart from active regions of a substrate for MOS transistors. This suppresses the influence of the increased gate length due to hammerhead and gate flaring. As a result, transistors TrA through TrF can have substantially the same finished gate length.
摘要翻译： 栅电极5A至5F形成为具有相同的几何形状，并且栅电极5A至5F的突出部分跨越隔离区延伸到杂质扩散区上。 栅电极5B和P型杂质扩散区7B6通过共用触点9A1连接到第一级布线M1H，栅电极5E和N型杂质扩散区7A6通过共用触点9A2连接到第一级 级互连M1I。 以这种方式，栅电极5A至5F的接触焊盘部分可以位于用于MOS晶体管的衬底的有源区域之外。 这抑制了由于锤头和栅极扩孔引起的栅极长度增加的影响。 结果，晶体管TrA至TrF可以具有基本相同的精加工栅极长度。
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公开(公告)号：US07709900B2
公开(公告)日：2010-05-04
申请号：US11892053
申请日：2007-08-20
IPC分类号： H01L23/62
CPC分类号： H01L21/76895 , H01L21/823475 , H01L27/0207
摘要： A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.
摘要翻译： 半导体器件包括半导体衬底; 扩散区，其形成在半导体衬底中并用作用于形成MIS晶体管的区域; 围绕扩散区域的元件隔离区域; 形成在扩散区域和元件隔离区域两侧的至少一个栅极导体膜包括位于扩散区域上的栅极电极部分和位于元件隔离区域上的栅极互连部件，并且栅极长度具有恒定的尺寸 方向; 以及覆盖所述栅电极的层间绝缘膜。 半导体器件还包括通过层间绝缘膜的栅极接触，连接到栅极互连部分，并且具有大于栅极互连部分的栅极长度方向的尺寸。
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7.发明申请Semiconductor integrated circuit designing method and library designing method 审中-公开半导体集成电路设计方法和图书馆设计方法公开(公告)号：US20060271902A1
公开(公告)日：2006-11-30
申请号：US11334506
申请日：2006-01-19
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method for designing a semiconductor integrated circuit includes: a step (a) of setting basic patterns including a plurality of active region/gate patterns each including a gate and an active region and a dummy gate while taking account of patterns of gates on the respective sides of each gate; a step (b) of forming a plurality of basic pattern combinations by combining some of the basic patterns; and a step (c) of forming a standard cell by combining some of the plurality of basic pattern combinations. The plurality of basic pattern combinations include a single transistor (large width), a single transistor (small width), and parallel connected N transistors (large width), for example.
摘要翻译： 一种用于设计半导体集成电路的方法包括：步骤（a），其设置包括多个有源区域/栅极图案的基本图案，每个有源区域/栅极图案包括栅极和有源区域以及伪栅极，同时考虑各个栅极的图案 每个门的边; 通过组合一些基本图案形成多个基本图案组合的步骤（b）; 以及通过组合多个基本图案组合中的一些来形成标准单元的步骤（c）。 多个基本图案组合包括例如单个晶体管（大宽度），单个晶体管（小宽度）和并联N个晶体管（大宽度）。
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公开(公告)号：US20130334608A1
公开(公告)日：2013-12-19
申请号：US13942546
申请日：2013-07-15
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L21/28088 , H01L21/823412 , H01L21/823425 , H01L21/82345 , H01L21/823456 , H01L21/823462 , H01L29/105 , H01L29/4966 , H01L29/665 , H01L29/7833
摘要： A semiconductor device includes a first transistor formed on a semiconductor substrate, and including a first channel region, and a first gate electrode formed on the first channel region, and a second transistor formed on the semiconductor substrate, and including a second channel region having a conductivity type identical to a conductivity type of the first channel region, and a second gate electrode formed on the second channel region and having a potential identical to a potential of the first gate electrode. A drain of the first transistor is electrically connected to a source of the second transistor. An absolute value of a threshold voltage of the first transistor is greater than an absolute value of a threshold voltage of the second transistor.
摘要翻译： 半导体器件包括形成在半导体衬底上并包括第一沟道区的第一晶体管和形成在第一沟道区上的第一栅极，以及形成在半导体衬底上的第二晶体管，并且包括第二沟道区， 导电类型与第一沟道区的导电类型相同，第二栅电极形成在第二沟道区上并具有与第一栅电极的电位相同的电位。 第一晶体管的漏极电连接到第二晶体管的源极。 第一晶体管的阈值电压的绝对值大于第二晶体管的阈值电压的绝对值。
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公开(公告)号：US07792663B2
公开(公告)日：2010-09-07
申请号：US11822781
申请日：2007-07-10
IPC分类号： G06F17/10
CPC分类号： G06F17/504 , G06F17/5022
摘要： A circuit simulation apparatus has a means to acquire data regarding a transistor, a model parameter generation unit for generating a model parameter representing effects of stress upon the transistor active region caused by the isolation region, and a simulation execution unit for evaluating characteristics of the transistor using a simulation program associated with the model parameter. The model parameter includes a term regarding width of the transistor active region, a term regarding width of the peripheral active region, and a term regarding width between the transistor active region and the peripheral active region.
摘要翻译： 电路模拟装置具有获取关于晶体管的数据的模块，用于产生表示由隔离区域引起的晶体管有源区上的应力的影响的模型参数的模型参数生成单元，以及用于评估晶体管的特性的模拟执行单元 使用与模型参数相关联的模拟程序。 模型参数包括关于晶体管有源区的宽度的术语，关于外围有源区的宽度的术语，以及关于晶体管有源区和外围有源区之间的宽度的项。
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公开(公告)号：US20100059801A1
公开(公告)日：2010-03-11
申请号：US12538534
申请日：2009-08-10
申请人： Masayuki Kamei , Kyouji Yamashita , Daisaku Ikoma
发明人： Masayuki Kamei , Kyouji Yamashita , Daisaku Ikoma
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/665 , H01L21/28088 , H01L21/28202 , H01L21/76897 , H01L29/41775 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843 , Y10S257/90
摘要： A semiconductor device includes a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; an offset spacer formed on a side surface of the gate electrode; an inner sidewall formed on the side surface of the gate electrode with the offset spacer interposed therebetween, and having an L-shaped cross section; and an insulating film formed to cover the gate electrode, the offset spacer, the inner sidewall, and a part of the semiconductor region located laterally outward from the inner sidewall. The offset spacer includes an inner offset spacer formed on the side surface of the gate electrode and an outer offset spacer formed to cover the side surface of the gate electrode and the inner offset spacer. The outer offset spacer is in contact with a top end and outer side surface of the inner offset spacer.
摘要翻译： 半导体器件包括形成在第一导电类型的半导体区域上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 形成在所述栅电极的侧面上的偏移间隔物; 在所述栅电极的侧面上形成有所述偏移间隔物的内侧壁，并具有L形截面; 以及绝缘膜，形成为覆盖从内侧壁侧向外侧的栅电极，偏移间隔件，内侧壁和半导体区域的一部分。 偏移间隔件包括形成在栅电极的侧表面上的内偏移间隔件和形成为覆盖栅电极的侧表面和内偏移间隔件的外偏移间隔件。 外部偏移间隔件与内部偏移间隔件的顶端和外侧表面接触。
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