公开(公告)号：US06197661B1

公开(公告)日：2001-03-06

申请号：US09300441

申请日：1999-04-28

申请人： Toru Mogami ,  Takashi Ogura

发明人： Toru Mogami ,  Takashi Ogura

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： A semiconductor device with the trench isolation structure is provided, in which the leakage current problem does not occur. This device is comprised ofa semiconductor substrate, an isolation trench formed in a surface region of the substrate and filled with first and second isolation dielectrics, an interlayer dielectric layer formed on the surface region of the substrate to cover the isolation trench, and a conductive layer formed on the interlayer dielectric layer to be overlapped with the isolation trench. The interlayer dielectric layer has a contact hole located near the isolation trench. The contact hole is formed by etching. The conductive layer is contacted with and electrically connected to a region of the substrate through the contact hole of the interlayer dielectric layer. The first isolation dielectric serves as a primary insulator. The second isolation dielectric serves as a secondary insulator. The first isolation dielectric has a pair of depressions located near a pair of top corners of the isolation trench. The pair of depressions of the first isolation dielectric are filled with the second isolation dielectric. The second dielectric is lower in etch rate than that of the first dielectric in the process for forming the contact hole.

摘要翻译： 提供了具有沟槽隔离结构的半导体器件，其中不会发生漏电流问题。 该器件由半导体衬底，形成在衬底的表面区域中并填充有第一和第二隔离电介质的隔离沟槽，形成在衬底的表面区域上以覆盖隔离沟槽的层间绝缘层和导电层 形成在层间电介质层上以与隔离沟槽重叠。 层间电介质层具有位于隔离沟槽附近的接触孔。 接触孔通过蚀刻形成。 导电层通过层间电介质层的接触孔与衬底的区域接触并电连接。 第一隔离绝缘体用作初级绝缘体。 第二隔离电介质用作次级绝缘体。 第一隔离电介质具有位于隔离沟槽的一对顶角附近的一对凹陷。 第一隔离电介质的一对凹陷填充有第二隔离电介质。 在形成接触孔的工艺中，第二电介质的蚀刻速率低于第一电介质。

公开(公告)号：US5929504A

公开(公告)日：1999-07-27

申请号：US97664

申请日：1998-06-16

申请人： Toru Mogami ,  Takashi Ogura

发明人： Toru Mogami ,  Takashi Ogura

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L29/00

CPC分类号： H01L21/76224

摘要： A semiconductor device with the trench isolation structure is provided, in which the leakage current problem does not occur. This device is comprised of a semiconductor substrate, an isolation trench formed in a surface region of the substrate and filled with first and second isolation dielectrics, an interlayer dielectric layer formed on the surface region of the substrate to cover the isolation trench, and a conductive layer formed on the interlayer dielectric layer to be overlapped with the isolation trench. The interlayer dielectric layer has a contact hole located near the isolation trench. The contact hole is formed by etching. The conductive layer is contacted with and electrically connected to a region of the substrate through the contact hole of the interlayer dielectric layer. The first isolation dielectric serves as a primary insulator. The second isolation dielectric serves as a secondary insulator. The first isolation dielectric has a pair of depressions, each having one side contiguous with one of the pair of top corners of the isolation trench. The pair of depressions of the first isolation dielectric are filled with the second isolation dielectric. The second dielectric is lower in etch rate than that of the first dielectric in the process for forming the contact hole.

摘要翻译： 提供了具有沟槽隔离结构的半导体器件，其中不会发生漏电流问题。 该器件由半导体衬底，形成在衬底的表面区域中并填充有第一和第二隔离电介质的隔离沟槽，形成在衬底的表面区域上以覆盖隔离沟槽的层间绝缘层和导电 层，形成在层间电介质层上以与隔离沟槽重叠。 层间电介质层具有位于隔离沟槽附近的接触孔。 接触孔通过蚀刻形成。 导电层通过层间电介质层的接触孔与衬底的区域接触并电连接。 第一隔离绝缘体用作初级绝缘体。 第二隔离电介质用作次级绝缘体。 第一隔离电介质具有一对凹陷，每个凹陷具有与隔离沟槽的一对顶角中的一个邻接的一侧。 第一隔离电介质的一对凹陷填充有第二隔离电介质。 在形成接触孔的工艺中，第二电介质的蚀刻速率低于第一电介质。

公开(公告)号：US06027977A

公开(公告)日：2000-02-22

申请号：US78811

申请日：1998-05-14

申请人： Toru Mogami

发明人： Toru Mogami

IPC分类号： H01L29/78 ,  H01L21/223 ,  H01L21/265 ,  H01L21/28 ,  H01L29/51 ,  H01L21/336 ,  H01L21/31

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L29/518 ,  H01L21/2236 ,  H01L21/26506

摘要： A fabrication method of a semiconductor device with the MIS structure is provided, which prevents the boron penetration phenomenon from occurring even if a gate insulator film is as thin as approximately 3 nm or less. After a silicon nitride film is formed on a semiconductor substrate, oxygen is doped into the silicon nitride film by a suitable process such as a thermal oxidation, ion implantation or plasma doping process, thereby forming an oxygen-doped silicon nitride film having an oxygen-rich region that extends along an interface between the oxygen-doped silicon nitride film and the substrate. The oxygen-rich region is higher in oxygen concentration than the remainder of the oxygen-doped silicon nitride film. At least part of the oxygen-doped silicon nitride film serves as a gate insulator film of a MISFET. Next, a gate electrode of the MISFET is formed on the oxygen-doped silicon nitride film. A dopant is selectively introduced into the substrate to form a pair of source/drain regions of the MISFET in the substrate at each side of the boron-doped gate electrode. Finally, the substrate is heat-treated to activate or anneal the dopant introduced into the substrate.

摘要翻译： 提供了具有MIS结构的半导体器件的制造方法，即使栅极绝缘膜薄至约3nm以下，也能够防止硼渗透现象。 在半导体衬底上形成氮化硅膜之后，通过诸如热氧化，离子注入或等离子体掺杂工艺的合适工艺将氧掺杂到氮化硅膜中，从而形成具有氧 - 氮的氮氧化物膜， 富氧区域沿着氧掺杂氮化硅膜和衬底之间的界面延伸。 富氧区域的氧浓度高于氧掺杂氮化硅膜的其余部分。 氧掺杂氮化硅膜的至少一部分用作MISFET的栅极绝缘膜。 接着，在氧掺杂氮化硅膜上形成MISFET的栅电极。 掺杂剂被选择性地引入到衬底中，以在硼掺杂栅电极的每一侧的衬底中形成MISFET的一对源/漏区。 最后，对衬底进行热处理以激活或退火引入到衬底中的掺杂剂。