公开(公告)号：US5179693A

公开(公告)日：1993-01-12

申请号：US416475

申请日：1989-10-03

申请人： Toshiaki Kitamura ,  Kazuyuki Shimizu ,  Yuji Oinaga ,  Katsumi Onishi

发明人： Toshiaki Kitamura ,  Kazuyuki Shimizu ,  Yuji Oinaga ,  Katsumi Onishi

IPC分类号： G06F9/38

CPC分类号： G06F9/3869 ,  G06F9/3836

摘要： A system for adjusting a performance of an information processing apparatus which provides a unit indicating a target performance value, a unit generating a corresponding performance control pulse in accordance with the target performance value, and an execution control unit which alternately sets an execution period and an execution inhibiting period in accordance with the performance control pulse. The unit which generates the performance control pulse sets a ratio of a pulse width and a pulse period of the performance control pulse coincide with the target performance value.

摘要翻译： 一种用于调整提供指示目标性能值的单元的信息处理设备的性能的系统，根据目标性能值产生相应的性能控制脉冲的单元，以及执行控制单元，其交替地设置执行周期和 执行禁止期间根据性能控制脉冲。 产生性能控制脉冲的单元设定性能控制脉冲的脉冲宽度和脉冲周期的比率与目标性能值一致。

公开(公告)号：US4910671A

公开(公告)日：1990-03-20

申请号：US844946

申请日：1986-03-27

申请人： Toshiaki Kitamura ,  Kazuyuki Shimizu ,  Yuji Oinaga ,  Katsumi Onishi

发明人： Toshiaki Kitamura ,  Kazuyuki Shimizu ,  Yuji Oinaga ,  Katsumi Onishi

IPC分类号： G06F9/30 ,  G06F1/04 ,  G06F9/00 ,  G06F9/38 ,  G06F15/00

CPC分类号： G06F9/3871 ,  G06F9/3836 ,  G06F9/3855

摘要： A system for adjusting a performance of an information processing apparatus which provides a unit indicating a target performance value, a unit generating a corresponding performance control pulse in accordance with the target performance value, and an execution control unit which alternately sets an execution period and an execution inhibiting period in accordance with the performance control pulse. The unit which generates the performance control pulse makes a ratio of a pulse width and a pulse period of the performance control pulse coincide with the target performance value.

摘要翻译： 一种用于调整提供指示目标性能值的单元的信息处理设备的性能的系统，根据目标性能值产生相应的性能控制脉冲的单元，以及执行控制单元，其交替地设置执行周期和 执行禁止期间根据性能控制脉冲。 产生性能控制脉冲的单元使得性能控制脉冲的脉冲宽度和脉冲周期的比率与目标性能值一致。

公开(公告)号：US5043868A

公开(公告)日：1991-08-27

申请号：US453193

申请日：1989-12-19

申请人： Toshiaki Kitamura ,  Yuji Oinaga ,  Katsumi Onishi

发明人： Toshiaki Kitamura ,  Yuji Oinaga ,  Katsumi Onishi

IPC分类号： G06F9/38

CPC分类号： G06F9/3824

摘要： A system for computer pipeline operation in which a plurality of instructions are executed in parallel by commencing, before the termination of execution of the preceding instruction, the execution of the present instruction, including a conflict detection unit, a data establishment indication unit, and a source data by-pass unit. The source data by-pass unit by-passes a source data to the processing stage which requires this source data immediately after conflict is detected between the result data of the preceding instruction and the source data of the present instruction and the establishment of the source data of the present instruction is detected.

摘要翻译： 一种用于计算机流水线操作的系统，其中在执行前一指令之前开始并行执行多条指令，执行本指令，包括冲突检测单元，数据建立指示单元和 源数据旁路单元。 源数据旁路单元将源数据旁路传递到处理阶段，该处理阶段在先前指令的结果数据与当前指令的源数据和源数据的建立之间检测到冲突之后立即需要该源数据 检测到本指令。

公开(公告)号：US4812970A

公开(公告)日：1989-03-14

申请号：US758664

申请日：1985-07-25

申请人： Toshiaki Kitamura ,  Katsumi Onishi ,  Yuji Oinaga

发明人： Toshiaki Kitamura ,  Katsumi Onishi ,  Yuji Oinaga

IPC分类号： G06F9/28 ,  G06F9/38

CPC分类号： G06F9/3867 ,  G06F9/28

摘要： According to the present invention, in a data processing unit which executes pipeline processings by developing an instruction into multiple flows through microprogram control, is a method provided where the microinstruction is divided into a part for controlling a first stage of pipeline and a part for controlling second and successive stages. The part for controlling the first stage is read simultaneously with the part for controlling the second and successive stages of the flow prior to the current flow. The present invention thus provides an advantage in that microprogram control can be employed for the first stage of the pipeline and resulting in a data processing unit which is capable of executing more flexible pipeline processings than the prior art can be formed. In an instructs a field for controlling the first stage of pipeline is separated from the fields for controlling the other stages and it is read at the same timing as that for reading the fields for controlling the second and successive stages of the flow just prior to the current flow. As a result, the first state of pipeline in the second and successive flow is controlled by microprogram control.

摘要翻译： PCT No.PCT / JP84 / 00533 Sec。 371日期1985年6月25日第 102（e）日期1985年6月25日PCT提交1984年11月8日PCT公布。 公开号WO85 / 02278 日期：1985年5月23日。根据本发明，在通过将指令发展成通过微程序控制的多个流程来执行流水线处理的数据处理单元中，提供了一种方法，其中将微指令分为用于控制第一阶段 管道和控制第二阶段和后续阶段的部分。 用于控制第一阶段的部分与用于控制当前流动之前的流的第二阶段和后续阶段的部分同时读取。 因此，本发明提供了一种优点，即微流程控制可以用于管道的第一级，并且导致能够执行比现有技术可以形成更灵活的流水线处理的数据处理单元。 在指令中，用于控制流水线的第一阶段的区域与用于控制其他阶段的区域分离，并且在与用于控制正好在流程之前控制流程的第二阶段和后续阶段的区域相同的时刻读取 当前流。 结果，第二和连续流中的第一流水线由微程序控制来控制。

公开(公告)号：US4742446A

公开(公告)日：1988-05-03

申请号：US682309

申请日：1984-12-17

申请人： Tetsuya Morioka ,  Tsutomu Tanaka ,  Katsumi Onishi ,  Yuji Oinaga

发明人： Tetsuya Morioka ,  Tsutomu Tanaka ,  Katsumi Onishi ,  Yuji Oinaga

IPC分类号： G06F12/00 ,  G06F12/04 ,  G06F12/08 ,  G06F12/06

CPC分类号： G06F12/0804

摘要： A computer system includes a processing unit; main storage; cache buffer storage provided between the processing unit and the main storage; and a store buffer device between the processing unit and main storage, receiving data identical to that stored in the cache buffer storage and control information in response to requests from the processing unit and transferring the data and control information to main storage. The transmission from the processing unit to the store buffer device and from the store buffer device to main storage are in a machine cycle. The store buffer device includes a controller, data register sets, each set including registers for receiving data to be stored in main storage, a byte mark register set of byte mark registers for information indicating storable data in the data registers, and an address register set of address registers for a starting store address in main storage for the data in the data registers. The number of data register sets is a plurality of times the bus width of the central processor. Each byte mark register has bits corresponding to the number of data register sets multiplied by the number of bytes in each data register.

摘要翻译： 计算机系统包括处理单元; 主要存储; 在处理单元和主存储器之间提供缓存缓冲存储器; 以及在处理单元和主存储器之间的存储缓冲器设备，响应于来自处理单元的请求接收与存储在高速缓存缓冲存储器和控制信息中的数据相同的数据，并将数据和控制信息传送到主存储器。 从处理单元到存储缓冲设备以及从存储缓冲设备到主存储器的传输在机器周期中。 存储缓冲装置包括控制器，数据寄存器组，每组包括用于接收存储在主存储器中的数据的寄存器，用于指示数据寄存器中的可存储数据的信息的字节标记寄存器的字节标记寄存器组，以及地址寄存器组 用于数据寄存器中的数据的主存储器中的起始存储地址的地址寄存器。 数据寄存器组的数量是中央处理器的总线宽度的多倍。 每个字节标记寄存器都有与数据寄存器组数相乘的位数乘以每个数据寄存器中的字节数。

公开(公告)号：US4852021A

公开(公告)日：1989-07-25

申请号：US198659

申请日：1988-05-19

申请人： Aiichiro Inoue ,  Katsumi Onishi ,  Yuji Oinaga ,  Kenichi Nojima

发明人： Aiichiro Inoue ,  Katsumi Onishi ,  Yuji Oinaga ,  Kenichi Nojima

IPC分类号： G06F15/16 ,  G06F13/00 ,  G06F15/17 ,  G06F15/173

CPC分类号： G06F15/17

摘要： A system for controlling the transfer of commands between processors of a multiprocessor system, including a single control unit connected to all the processors by separate information transfer lines. The control unit selects the processor generating a command transfer request signal in a predetermined priority order and receives the processor address from the selected processor. The receiving processor and predetermined transfer information are determined in accordance with the selected processor, the processor address, and the processor status information determined by the processor address. The predetermined transfer information is transferred to the receiving processor via an information transfer path established between the selected processor and the receiving processor.

摘要翻译： 一种用于控制多处理器系统的处理器之间的命令传送的系统，包括通过单独的信息传输线连接到所有处理器的单个控制单元。 控制单元选择处理器以预定优先级顺序生成命令传送请求信号，并从所选择的处理器接收处理器地址。 根据所选择的处理器，处理器地址和由处理器地址确定的处理器状态信息确定接收处理器和预定传送信息。 预定的传送信息经由在所选择的处理器和接收处理器之间建立的信息传送路径传送到接收处理器。

公开(公告)号：US4802113A

公开(公告)日：1989-01-31

申请号：US758665

申请日：1985-06-25

申请人： Katsumi Onishi ,  Yuji Oinaga ,  Kohei Otsuyama

发明人： Katsumi Onishi ,  Yuji Oinaga ,  Kohei Otsuyama

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3804 ,  G06F9/321

摘要： According to the present invention, an instruction address register unit I for reading instructions and an instruction address register unit II for indicating the address of the instruction being executed in the pipeline are provided independently. The address of a branching instruction is held in the instruction address register unit II until said instruction passes through the pipeline, the content of instruction address register unit I is updated when branching of the branching instruction is determined, and thereby delay in reading an instruction after 8 bytes at the branching address can be reduced.

摘要翻译： PCT No.PCT / JP84 / 00535 Sec。 371日期1985年6月25日第 102（e）日期1985年6月25日PCT提交1984年11月8日PCT公布。 第WO85 / 02279号公报 1985年5月23日。根据本发明，独立地提供用于读取指令的指令地址寄存器单元I和用于指示正​​在流水线中执行的指令的地址的指令地址寄存器单元II。 分支指令的地址被保持在指令地址寄存器单元II中，直到所述指令通过流水线，当分支指令的分支被确定时，指令地址寄存器单元I的内容被更新，从而延迟读取指令 可以减少分支地址处的8个字节。

公开(公告)号：US4701915A

公开(公告)日：1987-10-20

申请号：US763268

申请日：1985-08-07

申请人： Toshiaki Kitamura ,  Yuji Oinaga

发明人： Toshiaki Kitamura ,  Yuji Oinaga

IPC分类号： G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  G06F9/38 ,  G06F11/10 ,  G06F11/14 ,  G06F12/16 ,  G11C29/00

CPC分类号： G06F11/1008 ,  G06F11/1076 ,  G06F9/26 ,  G06F9/3861

摘要： An error recovery system in a data processor of the pipeline type, including control storage for storing instruction data, having an error correction and detection code adapted to the detection and correction of errors, for controlling the data processor. A parity check circuit checks instructions read from the control storage and stops at least a part of pipeline processing immediately upon the detection of an error. An error correction circuit corrects the error in the read instruction data and rewrites the instruction data into the control storage while the part of the pipeline processing is stopped.

摘要翻译： 流水线类型的数据处理器中的错误恢复系统，包括用于存储指令数据的控制存储器，具有适于检测和校正错误的纠错和检测代码，用于控制数据处理器。 奇偶校验电路检查从控制存储器读取的指令，并且在检测到错误时立即停止至少一部分流水线处理。 错误校正电路校正读取指令数据中的错误，并且在部分流水线处理停止时将指令数据重写到控制存储器中。

公开(公告)号：US4800490A

公开(公告)日：1989-01-24

申请号：US924329

申请日：1986-10-29

申请人： Tsutomu Tanaka ,  Yuji Oinaga

发明人： Tsutomu Tanaka ,  Yuji Oinaga

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0888 ,  G06F12/0859

摘要： A buffer storage control system is provided having a central processing unit having a buffer storage for storing a part of the content of a main storage, wherein, when a block transfer from the main storage to the buffer storage is carried out, data to be processed is transferred directly to an arithmetic unit or an instruction processing unit via a by-pass operation. The transferred data is then written into the buffer storage and only the portion written in a block can be read, even if not all of the data of one block is written into the buffer storage. During the period from the end of the by-pass operation to the end of the write operation into the buffer storage, with respect to data related to the by-pass operation and data transferred from the main storage, subsequent to the data related to the by-pass operation, the access to the buffer storage based upon a subsequent request for access is inhibited.

摘要翻译： 提供了具有中央处理单元的缓冲存储控制系统，该中央处理单元具有用于存储主存储器的内容的一部分的缓冲存储器，其中当执行从主存储器到缓冲存储器的块传送时，要处理的数据 通过旁路操作直接传送到运算单元或指令处理单元。 然后将传送的数据写入缓冲存储器，只有写入块的部分才能被读取，即使不是一个块的全部数据被写入缓冲存储器。 在从旁路操作结束到写操作结束到缓冲存储器的期间，对于与旁路操作有关的数据和从主存储器传送的数据，在与 旁路操作，禁止基于随后的访问请求对缓冲存储器的访问。

公开(公告)号：US5073871A

公开(公告)日：1991-12-17

申请号：US246087

申请日：1988-09-19

申请人： Nobuo Uchida ,  Yuji Oinaga ,  Mikio Itoh

发明人： Nobuo Uchida ,  Yuji Oinaga ,  Mikio Itoh

IPC分类号： G06F13/18

CPC分类号： G06F13/18

摘要： An access priority control system for a main storage for a computer, for controlling a signal transmission to the main storage upon receiving a plurality of storage access requests from at least one processor related to the main storage. The system includes a first access request port unit for holding at least temporarily a segment address of the storage access requests from the processor; a first control unit responsive to the output of the first access request port unit for checking bus conflict conditions and prohibition conditions for a destination storage segment determined by the address of the storage access request; a second access request port unit responsive to the output of the first control unit for holding at least temporarily an intra-segment address of the storage access request; and a second control unit responsive to the output of the second access request port unit for checking logical storage busy conditions in the storage segments.