公开(公告)号：US20180083018A1

公开(公告)日：2018-03-22

申请号：US15688826

申请日：2017-08-28

Applicant: Toshiba Memory Corporation

Inventor： Shigehiro YAMAKITA ,  Yoshiaki FUKUZUMI ,  Wataru SAKAMOTO ,  Satoshi NAGASHIMA

IPC: H01L27/11517 ,  H01L27/1157 ,  H01L27/105 ,  H01L27/11524 ,  H01L29/788

CPC classification number: H01L27/11517 ,  H01L27/1052 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/788

Abstract: A semiconductor memory device includes a semiconductor substrate, a stepped structure including a stepped part in which a plurality of first insulating layers and conductive layers are alternately stacked on a main surface of the semiconductor substrate, the conductive layers including first, second, and third conductive layers, a second insulating layer which covers the stepped structure, a first contact interconnection which penetrates the second insulating layer and the first conductive layer in a thickness direction of the semiconductor substrate and is electrically connected to the second conductive layer, and a second contact interconnection which penetrates the second insulating layer and the second conductive layer in the thickness direction of the semiconductor substrate and is electrically connected to the third conductive layer.