公开(公告)号：US20190181150A1

公开(公告)日：2019-06-13

申请号：US15929102

申请日：2019-02-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Wataru SAKAMOTO ,  Ryota SUZUKI ,  Tatsuya OKAMOTO ,  Tatsuya KATO ,  Fumitaka ARAI

IPC: H01L27/11556 ,  H01L29/792 ,  H01L29/66 ,  H01L29/06 ,  G11C16/04 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/11519

Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.

公开(公告)号：US20170352672A1

公开(公告)日：2017-12-07

申请号：US15686292

申请日：2017-08-25

Applicant: Toshiba Memory Corporation

Inventor： Wataru SAKAMOTO ,  Tatsuya KATO ,  Yuta WATANABE ,  Katsuyuki SEKINE ,  Toshiyuki IWAMOTO ,  Fumitaka ARAI

IPC: H01L27/11556 ,  H01L23/528

CPC classification number: H01L27/11556 ,  H01L23/528 ,  H01L27/11521

Abstract: A semiconductor memory device according to an embodiment includes first and second semiconductor pillars extending in a first direction and being arranged along a second direction, first and second interconnects extending in a third direction and being provided between the first semiconductor pillar and the second semiconductor pillar, a first electrode provided between the first semiconductor pillar and the first interconnect, a second electrode provided between the second semiconductor pillar and the second interconnect, third and fourth interconnects extending in the second direction, a first contact contacting the first semiconductor pillar and being connected to the third interconnect, and a second contact contacting the second semiconductor pillar and being connected to the fourth interconnect. The third and fourth interconnects each pass through both a region directly above the first semiconductor pillar and a region directly above the second semiconductor pillar.

公开(公告)号：US20170373082A1

公开(公告)日：2017-12-28

申请号：US15682996

申请日：2017-08-22

Applicant: Toshiba Memory Corporation

Inventor： Katsuyuki SEKINE ,  Tatsuya KATO ,  Fumitaka ARAI ,  Toshiyuki IWAMOTO ,  Yuta WATANABE ,  Wataru SAKAMOTO ,  Hiroshi ITOKAWA ,  Akio KANEKO

IPC: H01L27/11556 ,  H01L21/768 ,  H01L29/51 ,  H01L29/788 ,  H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L29/45 ,  H01L29/49 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/285 ,  H01L27/11519 ,  H01L29/10

CPC classification number: H01L27/11556 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02181 ,  H01L21/02271 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76801 ,  H01L27/11519 ,  H01L29/1037 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/456 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/515 ,  H01L29/517 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7883 ,  H01L29/7889

Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, a second insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, and a conductive film provided between the second electrode and the second insulating film, the conductive film not contacting the first insulating film.

公开(公告)号：US20180053774A1

公开(公告)日：2018-02-22

申请号：US15460536

申请日：2017-03-16

Applicant: Toshiba Memory Corporation

Inventor： Wataru SAKAMOTO

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L29/10 ,  H01L27/11565 ,  H01L27/11582 ,  H01L21/28

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/1037

Abstract: According to one embodiment, a semiconductor device includes a stacked body, a columnar portion, a first charge storage portion, and a second charge storage portion. The stacked body includes a plurality of electrode layers stacked in a first direction. The plurality of electrode layers includes a first electrode layer, and a second electrode layer. The columnar portion extends in the first direction in the stacked body. The first charge storage portion provides between the first electrode layer and the columnar portion. The second charge storage portion provides between the second electrode layer and the columnar portion. A first thickness in a second direction intersecting the first direction of the first charge storage portion between the first electrode layer and the columnar portion is thicker than a second thickness in the second direction of the second charge storage portion between the second electrode layer and the columnar portion.

公开(公告)号：US20210288057A1

公开(公告)日：2021-09-16

申请号：US17331147

申请日：2021-05-26

Applicant: Toshiba Memory Corporation

Inventor： Satoshi NAGASHIMA ,  Tatsuya KATO ,  Wataru SAKAMOTO

IPC: H01L27/11556 ,  G11C16/04 ,  G11C16/10 ,  H01L29/788 ,  H01L21/768 ,  H01L23/528 ,  H01L27/11521

Abstract: A semiconductor memory device according to an embodiment, includes a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction, two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction, and an electrode film disposed between each of the semiconductor pillars and each of the interconnects. The two interconnects are drivable independently from each other.

公开(公告)号：US20180350828A1

公开(公告)日：2018-12-06

申请号：US16049151

申请日：2018-07-30

Applicant: Toshiba Memory Corporation

Inventor： Wataru SAKAMOTO

IPC: H01L27/11556 ,  H01L21/28 ,  H01L27/11582 ,  H01L27/11565 ,  H01L29/10 ,  H01L27/11519

Abstract: According to one embodiment, a semiconductor device includes a stacked body, a columnar portion, a first charge storage portion, and a second charge storage portion. The stacked body includes a plurality of electrode layers stacked in a first direction. The plurality of electrode layers includes a first electrode layer, and a second electrode layer. The columnar portion extends in the first direction in the stacked body. The first charge storage portion provides between the first electrode layer and the columnar portion. The second charge storage portion provides between the second electrode layer and the columnar portion. A first thickness in a second direction intersecting the first direction of the first charge storage portion between the first electrode layer and the columnar portion is thicker than a second thickness in the second direction of the second charge storage portion between the second electrode layer and the columnar portion.

公开(公告)号：US20180083022A1

公开(公告)日：2018-03-22

申请号：US15822860

申请日：2017-11-27

Applicant: Toshiba Memory Corporation

Inventor： Tatsuya KATO ,  Wataru SAKAMOTO ,  Fumitaka ARAI

IPC: H01L27/11556 ,  H01L27/11548 ,  H01L27/11519

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11548

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first insulating film, a second insulating film, and a contact. The semiconductor pillars are provided on the substrate, extend in a first direction crossing an upper surface of the substrate, and are arranged along second and third directions being parallel to the upper surface and crossing each other. The first electrode films extend in the third direction. The second electrode film is provided between the semiconductor pillars and the first electrode films. The first insulating film is provided between the semiconductor pillars and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode films. The contact is provided at a position on the third direction of the semiconductor pillars and is connected to the first electrode films.

公开(公告)号：US20180083021A1

公开(公告)日：2018-03-22

申请号：US15700375

申请日：2017-09-11

Applicant: Toshiba Memory Corporation

Inventor： Wataru SAKAMOTO

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/11556 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11582

Abstract: A semiconductor device includes a stacked body 100, first insulating layers 45, a second insulating layer 46 and columnar portions CL. The stacked body 100 includes electrode layers 41 stacked with an insulating body interposed along a Z-direction. The first insulating layers 45 extend in an X-direction and are provided in the stacked body 100 from an upper end thereof to a lower end thereof. The second insulating layer extends in the X-direction and is provided in the stacked body 100 from the upper end to partway through the stacked body 100 between one of the first insulating layers 45 and another one of the first insulating layers 45. The columnar portion CL has a bowed configuration. The second insulating layer 46 is provided in a region B including a location of a maximum inner diameter Dm of the columnar portion CL.

公开(公告)号：US20210134822A1

公开(公告)日：2021-05-06

申请号：US17149029

申请日：2021-01-14

Applicant: Toshiba Memory Corporation

Inventor： Wataru SAKAMOTO

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L29/10 ,  H01L27/11565 ,  H01L27/11582 ,  H01L21/28 ,  H01L27/1157 ,  H01L27/11524

Abstract: According to one embodiment, a semiconductor device includes a stacked body, a columnar portion, a first charge storage portion, and a second charge storage portion. The stacked body includes a plurality of electrode layers stacked in a first direction. The plurality of electrode layers includes a first electrode layer, and a second electrode layer. The columnar portion extends in the first direction in the stacked body. The first charge storage portion provides between the first electrode layer and the columnar portion. The second charge storage portion provides between the second electrode layer and the columnar portion. A first thickness in a second direction intersecting the first direction of the first charge storage portion between the first electrode layer and the columnar portion is thicker than a second thickness in the second direction of the second charge storage portion between the second electrode layer and the columnar portion.

公开(公告)号：US20190252397A1

公开(公告)日：2019-08-15

申请号：US16333096

申请日：2016-09-21

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Wataru SAKAMOTO ,  Hiroshi NAKAKI ,  Hanae ISHIHARA

IPC: H01L27/11568 ,  H01L27/11578 ,  H01L27/11573 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L27/11573 ,  H01L27/11578 ,  H01L29/788 ,  H01L29/792

Abstract: A semiconductor device of the embodiment includes a stacked body, a first insulating layer, first and second staircase portions 2, and a second insulating layer 46. The stacked body includes a first electrode layer 41 (WLDD) and a second electrode layer 41 (SGD). The first and second staircase portions 2 are provided in a first end portion 101 a second end region 102. The second insulating layer 46 extends in the X-direction. The second insulating layer divides the second electrode layer 41 (SGD) in the X-direction direction. A length L1 in the X-direction of the second insulating layer 46 is longer than a length L2 in the x-direction of the second electrode layer 41 (SGD) and shorter than a length L3 in the X-direction of the first electrode layer 41 (WLDD).