公开(公告)号：US20210351235A1

公开(公告)日：2021-11-11

申请号：US17381911

申请日：2021-07-21

Applicant: Toshiba Memory Corporation

Inventor： Masahiro KIYOTOSHI ,  Akihito YAMAMOTO ,  Yoshio OZAWA ,  Fumitaka ARAI ,  Riichiro SHIROTA

IPC: H01L27/24 ,  H01L21/28 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L45/00 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/51

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.