公开(公告)号：US20210043546A1

公开(公告)日：2021-02-11

申请号：US17079736

申请日：2020-10-26

Applicant: Toshiba Memory Corporation

Inventor： Yasuhito YOSHIMIZU ,  Yoshiro SHIMOJO ,  Shinya ARAI

IPC: H01L23/48 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L23/522

Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.

公开(公告)号：US20210159237A1

公开(公告)日：2021-05-27

申请号：US17165169

申请日：2021-02-02

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yoshiro SHIMOJO

IPC: H01L27/11548 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. Portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member are formed as one body.

公开(公告)号：US20200043942A1

公开(公告)日：2020-02-06

申请号：US16228867

申请日：2018-12-21

Applicant: Toshiba Memory Corporation

Inventor： Yoshiro SHIMOJO ,  Tomoya Sanuki

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  G11C16/04

Abstract: According to one embodiment, a semiconductor memory device includes: a first interconnect layer including a first electrode that extends in a first direction and a second electrode that extends in a second direction and is in contact with one end of the first electrode; a second interconnect layer including a third electrode that is provided adjacently to the first electrode and a fourth electrode that is in contact with one end of the third electrode; a first semiconductor layer provided between the first electrode and the third electrode; a first charge storage layer provided between the first semiconductor layer and the first electrode; a second charge storage layer provided between the first semiconductor layer and the third electrode; and a first bit line provided above the first semiconductor layer and extending in the first direction.

公开(公告)号：US20200303395A1

公开(公告)日：2020-09-24

申请号：US16559380

申请日：2019-09-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keisuke NAKATSUKA ,  Yoshitaka KUBOTA ,  Tetsuaki UTSUMI ,  Yoshiro SHIMOJO ,  Ryota KATSUMATA

IPC: H01L27/11573 ,  H01L27/11578 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11551

Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.

公开(公告)号：US20200075461A1

公开(公告)日：2020-03-05

申请号：US16678007

申请日：2019-11-08

Applicant: Toshiba Memory Corporation

Inventor： Yasuhito YOSHIMIZU ,  Yoshiro SHIMOJO ,  Shinya ARAI

IPC: H01L23/48 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/522 ,  H01L27/11565

Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.

公开(公告)号：US20210399004A1

公开(公告)日：2021-12-23

申请号：US17462854

申请日：2021-08-31

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keisuke NAKATSUKA ,  Yoshitaka KUBOTA ,  Tetsuaki UTSUMI ,  Yoshiro SHIMOJO ,  Ryota KATSUMATA

IPC: H01L27/11573 ,  H01L27/11578 ,  H01L27/1157 ,  H01L27/11551 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565

Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.

公开(公告)号：US20190287985A1

公开(公告)日：2019-09-19

申请号：US16044775

申请日：2018-07-25

Applicant: Toshiba Memory Corporation

Inventor： Yoshiro SHIMOJO ,  Masahisa Sonoda

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/522 ,  G11C8/14

Abstract: A memory device includes a memory region, a connection region, an interconnection layer and a circuit. The memory region includes electrode layers and semiconductor layers. The electrode layers are stacked in a first direction, and the semiconductor layers extend in the first direction through the electrode layers. The connection region is surrounded with the memory region, and includes an insulating body and contact plugs. The insulating body has a thickness in the first direction thicker than a stacked width in the first direction of the electrode layers, and the contact plugs extending in the first direction through the insulating body. The interconnection layer includes interconnections electrically connected respectively to the electrode layers and some of the semiconductor layers. The electrode layers and the insulating body are positioned between the circuit and the interconnection layer in the first direction.