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公开(公告)号:US20190267392A1
公开(公告)日:2019-08-29
申请号:US16126259
申请日:2018-09-10
Applicant: Toshiba Memory Corporation
Inventor: Keisuke NAKATSUKA
IPC: H01L27/11582 , H01L29/51
Abstract: A semiconductor memory device includes a plurality of electrode films and a plurality of first insulating films stacked alternately along a first direction, a semiconductor member extending in the first direction, a charge storage member provided between the semiconductor member and the electrode films, and a second insulating film provided between the charge storage member and the electrode films. At least one of the plurality of first insulating films includes one or more types of a first material selected from the group consisting of silicon nitride, hafnium oxide, silicon oxynitride, and aluminum oxide.
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公开(公告)号:US20200091183A1
公开(公告)日:2020-03-19
申请号:US16351207
申请日:2019-03-12
Applicant: Toshiba Memory Corporation
Inventor: Keisuke NAKATSUKA
IPC: H01L27/11582 , H01L27/11565 , H01L27/1157
Abstract: A semiconductor memory device includes first structure bodies and second structure bodies arranged alternately along a first direction. The first structure body includes electrode films arranged along a second direction. The second structure body includes columnar members, first insulating members, and second insulating members. The columnar member includes a semiconductor member extending in the second direction and a charge storage member provided between the semiconductor member and the electrode film. The second insulating members are arranged along a third direction. Lengths in the first direction of the second insulating members are longer than lengths in the first direction of the first insulating members. Positions of the second insulating members in the third direction are different from each other between the second structure bodies adjacent to each other in the first direction. The columnar members and the first insulating members are arranged alternately between the second insulating members.
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公开(公告)号:US20200303403A1
公开(公告)日:2020-09-24
申请号:US16559389
申请日:2019-09-03
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Keisuke NAKATSUKA , Fumitaka ARAI
IPC: H01L27/11582 , H01L27/11556 , H01L23/528 , G11C16/14 , G11C16/10 , G11C16/26 , G11C16/04 , H01L27/11519 , H01L27/11565
Abstract: A semiconductor memory device includes a first block and a second block arranged adjacent to each other in a Y direction. Each of the first and second blocks includes conductive layers extended in an X direction, memory trenches between the conductive layers, memory pillars provided across two conductive layers with a memory trench interposed therebetween, and transistors provided between the memory pillars and the conductive layers. One of the conductive layers provided at an end of the first block in the Y direction is electrically connected to one of the conductive layers provided at an end of the second block.
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公开(公告)号:US20200286828A1
公开(公告)日:2020-09-10
申请号:US16564584
申请日:2019-09-09
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Keiji HOSOTANI , Fumitaka ARAI , Keisuke NAKATSUKA , Nobuyuki MOMO , Motohiko FUJIMATSU
IPC: H01L23/528 , H01L27/1157 , H01L27/11582 , H01L27/11565 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L23/522
Abstract: According to one embodiment, a semiconductor memory device includes: a first semiconductor layer including first to third portions which are arranged along a first direction and differ in position from one another in a second direction; a conductive layer including a fourth portion extending in the second direction and a fifth portion extending in the first direction; a first insulating layer between the fourth portion and the first semiconductor layer and between the fifth portion and the first semiconductor layer; a first contact plug coupled to the fourth portion; a second contact plug coupled to the first semiconductor layer in a region where the first insulating layer is formed; a first interconnect; and a first memory cell apart from the fifth portion in the first direction and storing information between the semiconductor layer and the first interconnect.
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公开(公告)号:US20180075892A1
公开(公告)日:2018-03-15
申请号:US15455906
申请日:2017-03-10
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Keisuke NAKATSUKA , Tsuneo INABA , Yutaka SHIRAI
IPC: G11C11/16
CPC classification number: G11C11/1673 , G11C7/04 , G11C7/065 , G11C11/1655 , G11C11/1657 , G11C11/1675 , G11C11/1693 , G11C11/5642 , G11C16/26 , G11C16/28
Abstract: According to one embodiment, a semiconductor memory device comprises: first to fourth memory cells, each of which is configured to have a first resistance state or a second resistance state; and a first circuit configured to output first data based on a first signal representing a resistance state of the first memory cell and a second signal representing a resistance state of the second memory cell, output second data based on the second signal and a third signal representing a resistance state of the third memory cell, and output third data based on the third signal and a fourth signal representing a resistance state of the fourth memory cell.
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公开(公告)号:US20200303395A1
公开(公告)日:2020-09-24
申请号:US16559380
申请日:2019-09-03
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Keisuke NAKATSUKA , Yoshitaka KUBOTA , Tetsuaki UTSUMI , Yoshiro SHIMOJO , Ryota KATSUMATA
IPC: H01L27/11573 , H01L27/11578 , H01L27/1157 , H01L27/11565 , H01L27/11519 , H01L27/11524 , H01L27/11529 , H01L27/11551
Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.
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公开(公告)号:US20200303389A1
公开(公告)日:2020-09-24
申请号:US16559363
申请日:2019-09-03
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Keisuke NAKATSUKA
IPC: H01L27/11556 , H01L23/528 , H01L27/11582 , G11C16/04
Abstract: A semiconductor memory device includes first conductive layers stacked on a substrate; second conductive layers stacked on the substrate and apart from the first conductive layer in a direction; third conductive layers stacked on the substrate and electrically connected to the first and second conductive layers; first insulating layers arranged in the direction to sandwich the first conductive layers; second insulating layers arranged in the direction to sandwich the second conductive layers; slit regions that sandwich the third conductive layers; and memory pillars disposed on the first and second insulating layers. The slit region is disposed between an end portion of one of the first insulating layers and an end portion of one of the second insulating layers.
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公开(公告)号:US20200176033A1
公开(公告)日:2020-06-04
申请号:US16562372
申请日:2019-09-05
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Keiji HOSOTANI , Fumitaka ARAI , Keisuke NAKATSUKA
IPC: G11C5/06 , H01L23/48 , H01L27/1157 , H01L27/11582 , H01L27/11565 , H01L27/11519 , H01L27/11524 , H01L27/11556 , G11C16/08 , G11C16/16 , G11C16/24 , G11C16/26 , G11C16/30
Abstract: According to one embodiment, a semiconductor memory device includes: a conductive layer including a first portion and a second portion electrically coupled to the first portion; a first contact plug electrically coupled to the first portion; a first semiconductor layer; a first insulating layer between the second portion and the first semiconductor layer, and between the first portion and the first semiconductor layer; a second contact plug coupled to the first semiconductor layer in a region in which the first insulating layer is formed; a first interconnect; and a first memory cell apart from the second portion in the second direction and storing information between the first semiconductor layer and the first interconnect.
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公开(公告)号:US20180102156A1
公开(公告)日:2018-04-12
申请号:US15835988
申请日:2017-12-08
Applicant: TOSHIBA MEMORY CORPORATION , SK HYNIX INC.
Inventor: Hisanori AIKAWA , Tatsuya KISHI , Keisuke NAKATSUKA , Satoshi INABA , Masaru TOKO , Keiji HOSOTANI , Jae Yun YI , Hong Ju SUH , Se Dong KIM
CPC classification number: G11C11/1673 , G11C5/063 , G11C8/08 , G11C8/12 , G11C11/161 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C2213/79 , G11C2213/82 , H01L27/228 , H01L27/2436 , H01L27/2463 , H01L43/08 , H01L45/06 , H01L45/1233 , H01L45/16 , H01L45/1675
Abstract: According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulating layer covering the transistor, a first conductive line connected to the first terminal and provided on the insulating layer, a second conductive line provided on the insulating layer, and a resistance change element connected between the second terminal and the second conductive line. The first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.
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公开(公告)号:US20210399004A1
公开(公告)日:2021-12-23
申请号:US17462854
申请日:2021-08-31
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Keisuke NAKATSUKA , Yoshitaka KUBOTA , Tetsuaki UTSUMI , Yoshiro SHIMOJO , Ryota KATSUMATA
IPC: H01L27/11573 , H01L27/11578 , H01L27/1157 , H01L27/11551 , H01L27/11519 , H01L27/11524 , H01L27/11529 , H01L27/11565
Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.
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