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    SEMICONDUCTOR MEMORY DEVICE
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210343737A1

    公开(公告)日：2021-11-04

    申请号：US17376856

    申请日：2021-07-15

    Applicant: Toshiba Memory Corporation

    Inventor： Tetsuaki UTSUMI

    IPC: H01L27/11568 ,  H01L27/11582 ,  H01L25/065 ,  G11C5/04 ,  H01L23/00 ,  H01L29/792 ,  H01L27/11578 ,  H01L21/822 ,  H01L21/28 ,  G11C29/02 ,  H01L27/11573 ,  H01L27/11575

    Abstract: A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction. A minimum period of an arrangement of the transistors is a first period. The stacked body includes electrode films. A configuration of a first portion of the stacked body is a staircase-like having terraces. A first region and a second region are set along the first direction in the first portion. A length in the first direction of the terrace disposed in the second region is longer than the first period. A length in the first direction of the terrace disposed in the first region is shorter than the first period.

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200251483A1

    公开(公告)日：2020-08-06

    申请号：US16857647

    申请日：2020-04-24

    Applicant: Toshiba Memory Corporation

    Inventor： Tetsuaki UTSUMI

    IPC: H01L27/11568 ,  H01L27/11582 ,  H01L25/065 ,  G11C5/04 ,  H01L23/00 ,  H01L29/792 ,  H01L27/11578 ,  H01L21/822 ,  H01L21/28 ,  G11C29/02 ,  H01L27/11573 ,  H01L27/11575

    Abstract: A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction. A minimum period of an arrangement of the transistors is a first period. The stacked body includes electrode films. A configuration of a first portion of the stacked body is a staircase-like having terraces. A first region and a second region are set along the first direction in the first portion. A length in the first direction of the terrace disposed in the second region is longer than the first period. A length in the first direction of the terrace disposed in the first region is shorter than the first period.

    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200126622A1

    公开(公告)日：2020-04-23

    申请号：US16535334

    申请日：2019-08-08

    Applicant: Toshiba Memory Corporation

    Inventor： Tetsuaki UTSUMI

    IPC: G11C16/04 ,  G11C11/56 ,  G11C16/08

    Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of transistors provided on a surface of the semiconductor substrate; and a first circuit electrically connected to gate electrodes of the plurality of transistors. The plurality of transistors include: a first transistor and a second transistor that are adjacent via an insulating region in a first direction; a third transistor that is adjacent to the first transistor and the second transistor via the insulating region in a second direction intersecting the first direction; and a fourth transistor that is adjacent to the first transistor and the second transistor via the insulating region in the second direction. The first circuit sets the first through fourth transistors to an ON state according to a first signal.

    SEMICONDUCTOR MEMORY DEVICE
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20180083020A1

    公开(公告)日：2018-03-22

    申请号：US15459489

    申请日：2017-03-15

    Applicant: Toshiba Memory Corporation

    Inventor： Tetsuaki UTSUMI

    IPC: H01L27/11548 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11524

    CPC classification number: H01L27/11548 ,  H01L23/5223 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11529

    Abstract: A semiconductor memory device includes first wires extending in a first direction; second wires provided in a first interconnect layer including the first wires, the second wires extending in the first direction along extension lines of the first wires respectively; third wires provided in a second interconnect layer different from the first interconnect layer; and transistors on/off controlling electrical connections between the first wires and the second wires through the third wires. The first and second wires are arranged respectively in a second direction crossing the first direction. The transistors are disposed in M stages (M is integer not less than 2) in the first direction, the M stages each including a transistor array aligned in the second direction. The first second wires are periodically arranged with the minimum period including M times N first wires (N is integer not less than 2) and M times N second wires.

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