公开(公告)号：US20190164979A1

公开(公告)日：2019-05-30

申请号：US16262827

申请日：2019-01-30

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tomoo HISHIDA ,  Sadatoshi MURAKAMI ,  Ryota KATSUMATA ,  Masao IWASE

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L21/8234 ,  H01L27/11575

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

公开(公告)号：US20210151465A1

公开(公告)日：2021-05-20

申请号：US17160563

申请日：2021-01-28

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi TAGAMI ,  Jun IIJIMA ,  Ryota KATSUMATA ,  Kazuyuki HIGASHI

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/522 ,  H01L27/1157 ,  H01L25/065 ,  H01L23/00

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

公开(公告)号：US20190326322A1

公开(公告)日：2019-10-24

申请号：US16460410

申请日：2019-07-02

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi TAGAMI ,  Jun IIJIMA ,  Ryota KATSUMATA ,  Kazuyuki HIGASHI

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/1157 ,  H01L23/00 ,  H01L23/522

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

公开(公告)号：US20180261623A1

公开(公告)日：2018-09-13

申请号：US15688561

申请日：2017-08-28

Applicant: Toshiba Memory Corporation

Inventor： Kazuyuki HIGASHI ,  Kazumichi TSUMURA ,  Ryota KATSUMATA ,  Fumitaka ARAI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11568 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor memory device includes a first memory cell array layer includes a first memory cell array region, in which memory cells are 3-dimensionally arrayed, and a first and second surface wiring layer connected to the memory cells. A second memory cell array layer includes second memory cell array region, in which memory cells are 3-dimensionally arrayed, and a third and fourth surface wiring layer connected to the second plurality of memory cells. The first memory cell array layer and the second memory cell array layer are bonded to each other such that the second surface wiring layer and the third surface wiring layer face each other and are bonded to each other. The first and second memory cell array regions overlap each other as viewed from a direction orthogonal to a layer plane.

公开(公告)号：US20200350291A1

公开(公告)日：2020-11-05

申请号：US16916979

申请日：2020-06-30

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi TAGAMI ,  Ryota KATSUMATA ,  Jun IIJIMA ,  Tetsuya SHIMIZU ,  Takamasa USUI ,  Genki FUJITA

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

公开(公告)号：US20180006042A1

公开(公告)日：2018-01-04

申请号：US15708033

申请日：2017-09-18

Applicant: Toshiba Memory Corporation

Inventor： Tomoo HISHIDA ,  Sadatoshi MURAKAMI ,  Ryota KATSUMATA ,  Masao IWASE

IPC: H01L27/1157 ,  H01L21/8234 ,  H01L27/11575 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L21/823437 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

公开(公告)号：US20170373080A1

公开(公告)日：2017-12-28

申请号：US15677361

申请日：2017-08-15

Applicant: Toshiba Memory Corporation

Inventor： Yoshihiro AKUTSU ,  Ryota KATSUMATA

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/768 ,  H01L21/74 ,  H01L27/1157 ,  H01L23/535 ,  H01L27/11573 ,  H01L27/11578

CPC classification number: H01L27/11556 ,  H01L21/743 ,  H01L21/76889 ,  H01L23/535 ,  H01L25/00 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.

公开(公告)号：US20210217755A1

公开(公告)日：2021-07-15

申请号：US17214710

申请日：2021-03-26

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tomoo HISHIDA ,  Sadatoshi MURAKAMI ,  Ryota KATSUMATA ,  Masao IWASE

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/11575 ,  H01L21/8234

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

公开(公告)号：US20200303395A1

公开(公告)日：2020-09-24

申请号：US16559380

申请日：2019-09-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keisuke NAKATSUKA ,  Yoshitaka KUBOTA ,  Tetsuaki UTSUMI ,  Yoshiro SHIMOJO ,  Ryota KATSUMATA

IPC: H01L27/11573 ,  H01L27/11578 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11551

Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.

公开(公告)号：US20190312012A1

公开(公告)日：2019-10-10

申请号：US16390639

申请日：2019-04-22

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi TAGAMI ,  Ryota KATSUMATA ,  Jun IIJIMA ,  Tetsuya SHIMIZU ,  Takamasa USUI ,  Genki FUJITA

IPC: H01L25/065 ,  H01L25/00 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11556 ,  H01L23/00

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.