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公开(公告)号：US20100181647A1
公开(公告)日：2010-07-22
申请号：US12750402
申请日：2010-03-30
CPC分类号： H01L23/5223 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved.
摘要翻译： 在本发明中，电容元件的下电极的上阻挡膜和与其形成的相同层中的金属互连层的上阻挡膜的膜厚比其他的上阻挡膜的膜厚更厚 金属互连层。 此外，在本发明中，电容元件的下电极的上阻挡膜的膜厚控制在110nm以上，更优选为160nm以上。 不会发生由于上阻挡膜中的裂纹引起的电容电介质膜的电介质电压的降低，并且可以使电容电介质膜的沉积温度更高，使得具有高性能和高的MIM电容器的半导体器件 可以实现电容，其中电容电介质膜的介电电压得到改善。
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公开(公告)号：US20100320568A1
公开(公告)日：2010-12-23
申请号：US12873668
申请日：2010-09-01
申请人： Tsuyoshi FUJIWARA , Toshinori IMAI , Takeshi SAIKAWA , Yoshihiro KAWASAKI , Mitsuhiro TOYA , Shunji MORI , Yoshiyuki OKABE
发明人： Tsuyoshi FUJIWARA , Toshinori IMAI , Takeshi SAIKAWA , Yoshihiro KAWASAKI , Mitsuhiro TOYA , Shunji MORI , Yoshiyuki OKABE
IPC分类号： H01L29/92
CPC分类号： H01L28/91 , H01L27/10852 , H01L28/87
摘要： Provided is a technology capable of reducing parasitic capacitance of a capacitor while reducing the space occupied by the capacitor. A stacked structure is obtained by forming, over a capacitor composed of a lower electrode, a capacitor insulating film and an intermediate electrode, another capacitor composed of the intermediate electrode, another capacitor insulating film and an upper electrode. Since the intermediate electrode has a step difference, each of the distance between the intermediate electrode and lower electrode and the distance between the intermediate electrode and upper electrode in a region other than the capacitor formation region becomes greater than that in the capacitor formation region. For example, the lower electrode is brought into direct contact with the capacitor insulating film in the capacitor formation region, while the lower electrode is not brought into direct contact with the capacitor insulating film in the region other than the capacitor formation region.
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公开(公告)号：US20100013568A1
公开(公告)日：2010-01-21
申请号：US12565963
申请日：2009-09-24
申请人： Tsuyoshi FUJIWARA , Toshinori IMAI , Takeshi SAIKAWA , Yoshihiro KAWASAKI , Mitsuhiro TOYA , Shunji MORI , Yoshiyuki OKABE
发明人： Tsuyoshi FUJIWARA , Toshinori IMAI , Takeshi SAIKAWA , Yoshihiro KAWASAKI , Mitsuhiro TOYA , Shunji MORI , Yoshiyuki OKABE
CPC分类号： H01L28/91 , H01L27/10852 , H01L28/87
摘要： Provided is a technology capable of reducing parasitic capacitance of a capacitor while reducing the space occupied by the capacitor. A stacked structure is obtained by forming, over a capacitor composed of a lower electrode, a capacitor insulating film and an intermediate electrode, another capacitor composed of the intermediate electrode, another capacitor insulating film and an upper electrode. Since the intermediate electrode has a step difference, each of the distance between the intermediate electrode and lower electrode and the distance between the intermediate electrode and upper electrode in a region other than the capacitor formation region becomes greater than that in the capacitor formation region. For example, the lower electrode is brought into direct contact with the capacitor insulating film in the capacitor formation region, while the lower electrode is not brought into direct contact with the capacitor insulating film in the region other than the capacitor formation region.
摘要翻译： 提供了一种能够减小电容器的寄生电容同时减小电容器所占空间的技术。 通过在由下电极构成的电容器，电容绝缘膜和中间电极上形成电容器，由中间电极，另一电容绝缘膜和上电极构成的另一电容器形成堆叠结构。 由于中间电极具有台阶差，所以在电容器形成区域以外的区域中，中间电极和下部电极之间的距离以及中间电极和上部电极之间的距离变得比电容器形成区域的大。 例如，下电极与电容器形成区域中的电容绝缘膜直接接触，而在电容器形成区域以外的区域中，下电极不与电容器绝缘膜直接接触。
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公开(公告)号：US20120009756A1
公开(公告)日：2012-01-12
申请号：US13238056
申请日：2011-09-21
IPC分类号： H01L21/02
CPC分类号： H01L23/5228 , H01L27/0688 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to the present invention includes: a lower-surface oxidation preventing insulating film formed on a lower surface of a metal resistor element; an upper-surface oxidation preventing insulating film formed on an upper surface of the metal resistor element; and a side-surface oxidation preventing insulating film formed only near a side surface of the metal resistor element by performing anisotropic etching after being deposited on a whole surface of a wafer in a process separated from the lower-surface oxidation preventing insulating film and the upper-surface oxidation preventing insulating film. According to the present invention, it is possible to prevent the increase of the resistance value due to the oxidation of the metal resistor element and also to prevent the increase of the parasitic capacitance between metal wiring layers without complicating the fabrication process.
摘要翻译： 根据本发明的半导体器件包括：形成在金属电阻器元件的下表面上的下表面的氧化防止绝缘膜; 形成在所述金属电阻元件的上表面上的上表面氧化防止绝缘膜; 以及侧面氧化防止绝缘膜，其仅在金属电阻元件的侧面附近形成，在与下表面的氧化防止绝缘膜分离的工序中沉积在晶片的整个表面上，进行各向异性蚀刻 表面氧化防止绝缘膜。 根据本发明，可以防止由于金属电阻元件的氧化引起的电阻值的增加，并且还可以防止金属布线层之间的寄生电容的增加，而不会使制造工艺复杂化。
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