公开(公告)号：US07981761B2

公开(公告)日：2011-07-19

申请号：US12750402

申请日：2010-03-30

申请人： Toshinori Imai ,  Tsuyoshi Fujiwara ,  Hiroshi Ashihara ,  Akira Ootaguro ,  Yoshihiro Kawasaki

发明人： Toshinori Imai ,  Tsuyoshi Fujiwara ,  Hiroshi Ashihara ,  Akira Ootaguro ,  Yoshihiro Kawasaki

IPC分类号： H01L21/20 ,  H01L21/8242 ,  H01L21/4763 ,  H01L21/70 ,  H01L21/02 ,  H01L23/48 ,  H01L23/52 ,  H01L23/28

CPC分类号： H01L23/5223 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

摘要： In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved.

摘要翻译： 在本发明中，电容元件的下电极的上阻挡膜和与其形成的相同层中的金属互连层的上阻挡膜的膜厚比其他的上阻挡膜的膜厚更厚 金属互连层。 此外，在本发明中，电容元件的下电极的上阻挡膜的膜厚控制在110nm以上，更优选为160nm以上。 不会发生由于上阻挡膜中的裂纹引起的电容电介质膜的电介质电压的降低，并且可以使电容电介质膜的沉积温度更高，使得具有高性能和高的MIM电容器的半导体器件 可以实现电容，其中电容电介质膜的介电电压得到改善。

公开(公告)号：US07582901B2

公开(公告)日：2009-09-01

申请号：US11059651

申请日：2005-02-17

申请人： Kenichi Takeda ,  Tsuyoshi Fujiwara ,  Toshinori Imai ,  Tsuyoshi Ishikawa ,  Toshiyuki Mine ,  Makoto Miura

发明人： Kenichi Takeda ,  Tsuyoshi Fujiwara ,  Toshinori Imai ,  Tsuyoshi Ishikawa ,  Toshiyuki Mine ,  Makoto Miura

IPC分类号： H01L29/76

CPC分类号： H01L28/40 ,  H01L21/76838

摘要： An MIM capacitor using a high-permittivity dielectric film such as tantalum oxide. The MIM capacitor includes an upper electrode, a dielectric film, and a lower electrode. A second dielectric film and the dielectric film are formed between the upper electrode and the lower electrode, at the end of the MIM capacitor. The second dielectric film is formed to have an opening at the top of the lower electrode. The dielectric film abuts the lower electrode via the opening. The upper electrode is formed on the dielectric film. The upper electrode and the dielectric film are formed in such a manner as to embrace the opening entirely, and the second dielectric film and the lower electrode are formed so that the respective widths are the same as, or greater than, the widths of the upper electrode and the dielectric film.

摘要翻译： 使用诸如氧化钽的高介电常数电介质膜的MIM电容器。 MIM电容器包括上电极，电介质膜和下电极。 在MIM电容器的端部，在上电极和下电极之间形成第二电介质膜和电介质膜。 第二电介质膜形成为在下电极的顶部具有开口。 电介质膜经由开口抵接下电极。 上电极形成在电介质膜上。 上部电极和电介质膜以完全包围开口的方式形成，并且第二电介质膜和下部电极形成为使得各个宽度与上部的宽度相同或更大 电极和电介质膜。

公开(公告)号：US20080233736A1

公开(公告)日：2008-09-25

申请号：US12127564

申请日：2008-05-27

申请人： Naofumi Ohashi ,  Junji Noguchi ,  Toshinori Imai ,  Hizuru Yamaguchi ,  Nobuo Owada ,  Kenji Hinode ,  Yoshio Homma ,  Seiichi Kondo

发明人： Naofumi Ohashi ,  Junji Noguchi ,  Toshinori Imai ,  Hizuru Yamaguchi ,  Nobuo Owada ,  Kenji Hinode ,  Yoshio Homma ,  Seiichi Kondo

IPC分类号： H01L21/4763

CPC分类号： H01L21/0209 ,  G09G5/399 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/76838 ,  H01L21/7684 ,  Y10S438/906

摘要： In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

摘要翻译： 为了提供通过化学机械抛光（CMP）方法形成的金属配线的防腐蚀技术，根据本发明的半导体集成电路器件的制造方法包括以下步骤：形成Cu（或Cu合金）的金属层 含有Cu作为主要成分），然后通过化学机械抛光（CMP）方法平坦化金属层以形成金属布线; 防止晶片的平面化主面在金属布线的表面上形成疏水性保护膜; 将晶圆的防腐主面浸入或保持湿润状态，使其不会变干; 并将晶片的主要表面保持在潮湿状态。

公开(公告)号：US20060141792A1

公开(公告)日：2006-06-29

申请号：US11357181

申请日：2006-02-21

申请人： Naofumi Ohashi ,  Junji Noguchi ,  Toshinori Imai ,  Hizuru Yamaguchi ,  Nobuo Owada ,  Kenji Hinode ,  Yoshio Homma ,  Seiichi Kondo

发明人： Naofumi Ohashi ,  Junji Noguchi ,  Toshinori Imai ,  Hizuru Yamaguchi ,  Nobuo Owada ,  Kenji Hinode ,  Yoshio Homma ,  Seiichi Kondo

IPC分类号： H01L21/44

CPC分类号： H01L21/0209 ,  G09G5/399 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/76838 ,  H01L21/7684 ,  Y10S438/906

摘要： In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP). method, a process for manufacturing. a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

摘要翻译： 为了提供通过化学机械抛光（CMP）形成的金属配线的防腐蚀技术。 方法，制造方法。 根据本发明的半导体集成电路器件包括以下步骤：在晶片的主面上形成Cu（或含有Cu作为主要成分的Cu合金）的金属层，然后通过化学机械抛光使金属层平坦化 （CMP）方法形成金属布线; 防止晶片的平面化主面在金属布线的表面上形成疏水性保护膜; 将晶圆的防腐主面浸入或保持湿润状态，使其不会变干; 并将晶片的主要表面保持在潮湿状态。

公开(公告)号：US06982200B2

公开(公告)日：2006-01-03

申请号：US10748286

申请日：2003-12-31

申请人： Junji Noguchi ,  Toshinori Imai ,  Tsuyoshi Fujiwara

发明人： Junji Noguchi ,  Toshinori Imai ,  Tsuyoshi Fujiwara

IPC分类号： H01L21/8242

CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76832 ,  H01L21/76838 ,  H01L23/5223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method of manufacturing a semiconductor device which has reliable buried interconnects (wirings) and a reliable MIM capacitor. An interconnect and a capacitor bottom electrode are formed inside a hole made in six insulation films. Then a barrier insulation film is formed on the uppermost film (of the above six insulation films) including the interconnect and the top face of the bottom electrode. After two insulation films are formed above the barrier insulation film, a hole is made in the two insulation films and a capacitor top electrode is buried in that hole. The barrier insulation film also functions as a capacity insulation film for the capacitor. Then, after three other insulation films are formed on the upper film (of the above two insulation films) including the top face of the top electrode, a hole is made in the barrier insulation film, the two insulation films, and the three other insulation films, and another interconnect is buried in that hole.

摘要翻译： 公开了一种具有可靠的埋地互连（布线）和可靠的MIM电容器的半导体器件的制造方法。 在由六个绝缘膜制成的孔内形成互连和电容器底部电极。 然后在包括互连件和底部电极的顶面的最上面的膜（上述六个绝缘膜）上形成阻挡绝缘膜。 在阻挡绝缘膜上方形成两个绝缘膜之后，在两个绝缘膜中形成孔，并且在该孔中埋置电容器顶部电极。 阻挡绝缘膜还用作电容器的电容绝缘膜。 然后，在上电极（上述两个绝缘膜）的上部膜上形成三个绝缘膜之后，在隔离绝缘膜，两个绝缘膜和三个绝缘层中形成一个孔 电影，另一个互连被埋在那个洞里。

公开(公告)号：US20050212082A1

公开(公告)日：2005-09-29

申请号：US11059651

申请日：2005-02-17

申请人： Kenichi Takeda ,  Tsuyoshi Fujiwara ,  Toshinori Imai ,  Tsuyoshi Ishikawa ,  Toshiyuki Mine ,  Makoto Miura

发明人： Kenichi Takeda ,  Tsuyoshi Fujiwara ,  Toshinori Imai ,  Tsuyoshi Ishikawa ,  Toshiyuki Mine ,  Makoto Miura

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L27/108

CPC分类号： H01L28/40 ,  H01L21/76838

摘要： An MIM capacitor using a high-permittivity dielectric film such as tantalum oxide. The MIM capacitor includes an upper electrode, a dielectric film, and a lower electrode. A second dielectric film and the dielectric film are formed between the upper electrode and the lower electrode, at the end of the MIM capacitor. The second dielectric film is formed to have an opening at the top of the lower electrode. The dielectric film abuts the lower electrode via the opening. The upper electrode is formed on the dielectric film. The upper electrode and the dielectric film are formed in such a manner as to embrace the opening entirely, and the second dielectric film and the lower electrode are formed so that the respective widths are the same as, or greater than, the widths of the upper electrode and the dielectric film.

摘要翻译： 使用诸如氧化钽的高介电常数电介质膜的MIM电容器。 MIM电容器包括上电极，电介质膜和下电极。 在MIM电容器的端部，在上电极和下电极之间形成第二电介质膜和电介质膜。 第二电介质膜形成为在下电极的顶部具有开口。 电介质膜经由开口抵接下电极。 上电极形成在电介质膜上。 上部电极和电介质膜以完全包围开口的方式形成，并且第二电介质膜和下部电极形成为使得各个宽度与上部的宽度相同或更大 电极和电介质膜。

公开(公告)号：US06800557B2

公开(公告)日：2004-10-05

申请号：US10369716

申请日：2003-02-21

申请人： Naofumi Ohashi ,  Junji Noguchi ,  Toshinori Imai ,  Hizuru Yamaguchi ,  Nobuo Owada ,  Kenji Hinode ,  Yoshio Homma ,  Seiichi Kondo

发明人： Naofumi Ohashi ,  Junji Noguchi ,  Toshinori Imai ,  Hizuru Yamaguchi ,  Nobuo Owada ,  Kenji Hinode ,  Yoshio Homma ,  Seiichi Kondo

IPC分类号： H01L21302

CPC分类号： H01L21/0209 ,  G09G5/399 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/76838 ,  H01L21/7684 ,  Y10S438/906

摘要： In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

摘要翻译： 为了提供通过化学机械抛光（CMP）方法形成的金属配线的防腐蚀技术，根据本发明的半导体集成电路器件的制造方法包括以下步骤：形成Cu（或Cu合金）的金属层 含有Cu作为主要成分），然后通过化学机械抛光（CMP）方法平坦化金属层以形成金属布线; 防止晶片的平面化主面在金属布线的表面上形成疏水性保护膜; 将晶圆的防腐主面浸入或保持湿润状态，使其不会变干; 并将晶片的主要表面保持在潮湿状态。

公开(公告)号：US06561875B1

公开(公告)日：2003-05-13

申请号：US09558593

申请日：2000-04-26

申请人： Yoshio Homma ,  Noriyuki Sakuma ,  Naofumi Ohashi ,  Toshinori Imai

发明人： Yoshio Homma ,  Noriyuki Sakuma ,  Naofumi Ohashi ,  Toshinori Imai

IPC分类号： B24B2900

CPC分类号： B24B49/006 ,  B24B37/042 ,  B24B49/16 ,  B24B57/02

摘要： The apparatus and method for producing a substrate whose surface includes a metallic wire by polishing the substrate surface. A polishing liquid is supplied to a clearance between the substrate and the surface of a polishing pad. The polishing liquid includes an acid which dissolves the oxidized part of the substrate surface and is substantially free of solid abrasive powder. A relative movement is generated between the substrate surface and the polishing pad surface while the substrate surface is pressed against the polishing pad surface while the polishing liquid is supplied so that the dissolved oxidized part of the substrates surface can be removed from the substrate.

摘要翻译： 通过研磨基板表面来制造表面包括金属线的基板的装置和方法。 将研磨液供给到基板与研磨垫的表面之间的间隙。 抛光液包括溶解基材表面的氧化部分并基本上不含固体磨料粉末的酸。 当衬底表面被压靠在抛光垫表面上时，在衬底表面和抛光垫表面之间产生相对运动，同时提供抛光液体，使得可以从衬底去除基底表面的溶解的氧化部分。

公开(公告)号：US06495466B2

公开(公告)日：2002-12-17

申请号：US09823975

申请日：2001-04-03

申请人： Kazusato Hara ,  Keisuke Funatsu ,  Toshinori Imai ,  Junji Noguchi ,  Naohumi Ohashi

发明人： Kazusato Hara ,  Keisuke Funatsu ,  Toshinori Imai ,  Junji Noguchi ,  Naohumi Ohashi

IPC分类号： H01L2100

CPC分类号： H01L21/76873 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76874

摘要： Over a plug, a stopper insulating film made of an organic film is formed, followed by successive formation of an insulating film and a hard mask. In the presence of a patterned resist film, the hard mask is dry etched, whereby an interconnection groove pattern is transferred thereto. By ashing with oxygen plasma, the resist film is removed to form the interconnection-groove-pattern-transferred hard mask. At this time, the organic film constituting the stopper insulating film has been covered with the insulating film. Then, the insulating film, stopper insulating film and hard mask are removed to form the groove pattern of interconnection. Hydrogen annealing may be conducted after formation of the plug, or the stopper insulating film may be formed over the plug via an adhesion layer.

摘要翻译： 在塞子上形成由有机膜制成的阻挡绝缘膜，随后形成绝缘膜和硬掩模。 在图案化抗蚀剂膜的存在下，硬掩模被干蚀刻，由此将互连槽图案转印到其上。 通过用氧等离子体灰化，去除抗蚀剂膜以形成互连凹槽图案转印的硬掩模。 此时，构成阻挡绝缘膜的有机膜被绝缘膜覆盖。 然后，去除绝缘膜，阻挡绝缘膜和硬掩模以形成互连的凹槽图案。 可以在形成塞子之后进行氢退火，或者可以通过粘合层在塞子上形成塞子绝缘膜。

公开(公告)号：US07510970B2

公开(公告)日：2009-03-31

申请号：US11357181

申请日：2006-02-21

申请人： Naofumi Ohashi ,  Junji Noguchi ,  Toshinori Imai ,  Hizuru Yamaguchi ,  Nobuo Owada ,  Kenji Hinode ,  Yoshio Homma ,  Seiichi Kondo

发明人： Naofumi Ohashi ,  Junji Noguchi ,  Toshinori Imai ,  Hizuru Yamaguchi ,  Nobuo Owada ,  Kenji Hinode ,  Yoshio Homma ,  Seiichi Kondo

IPC分类号： H01L21/44

CPC分类号： H01L21/0209 ,  G09G5/399 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/76838 ,  H01L21/7684 ,  Y10S438/906

摘要： In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.