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公开(公告)号：US20080203531A1
公开(公告)日：2008-08-28
申请号：US12024140
申请日：2008-02-01
CPC分类号： H01L23/5223 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved.
摘要翻译： 在本发明中，电容元件的下电极的上阻挡膜和与其形成的相同层中的金属互连层的上阻挡膜的膜厚比其他的上阻挡膜的膜厚更厚 金属互连层。 此外，在本发明中，电容元件的下电极的上阻挡膜的膜厚控制在110nm以上，更优选为160nm以上。 不会发生由于上阻挡膜中的裂纹引起的电容电介质膜的电介质电压的降低，并且可以使电容电介质膜的沉积温度更高，使得具有高性能和高的MIM电容器的半导体器件 可以实现电容，其中电容电介质膜的介电电压得到改善。
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公开(公告)号：US07981761B2
公开(公告)日：2011-07-19
申请号：US12750402
申请日：2010-03-30
IPC分类号： H01L21/20 , H01L21/8242 , H01L21/4763 , H01L21/70 , H01L21/02 , H01L23/48 , H01L23/52 , H01L23/28
CPC分类号： H01L23/5223 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved.
摘要翻译： 在本发明中，电容元件的下电极的上阻挡膜和与其形成的相同层中的金属互连层的上阻挡膜的膜厚比其他的上阻挡膜的膜厚更厚 金属互连层。 此外，在本发明中，电容元件的下电极的上阻挡膜的膜厚控制在110nm以上，更优选为160nm以上。 不会发生由于上阻挡膜中的裂纹引起的电容电介质膜的电介质电压的降低，并且可以使电容电介质膜的沉积温度更高，使得具有高性能和高的MIM电容器的半导体器件 可以实现电容，其中电容电介质膜的介电电压得到改善。
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公开(公告)号：US20100181647A1
公开(公告)日：2010-07-22
申请号：US12750402
申请日：2010-03-30
CPC分类号： H01L23/5223 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved.
摘要翻译： 在本发明中，电容元件的下电极的上阻挡膜和与其形成的相同层中的金属互连层的上阻挡膜的膜厚比其他的上阻挡膜的膜厚更厚 金属互连层。 此外，在本发明中，电容元件的下电极的上阻挡膜的膜厚控制在110nm以上，更优选为160nm以上。 不会发生由于上阻挡膜中的裂纹引起的电容电介质膜的电介质电压的降低，并且可以使电容电介质膜的沉积温度更高，使得具有高性能和高的MIM电容器的半导体器件 可以实现电容，其中电容电介质膜的介电电压得到改善。
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4.发明授权公开(公告)号：US06696357B2
公开(公告)日：2004-02-24
申请号：US10195716
申请日：2002-07-16
IPC分类号： H01L2160
CPC分类号： H01L24/05 , H01L21/76838 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05558 , H01L2224/05624 , H01L2224/45015 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： Peeling between a bonding pad and an insulating film which underlies the bonding pad is to be prevented. A laminate film constituted mainly by W which is higher in mechanical strength than a wiring layer using an Al alloy film as a main conductive layer and than a bonding pad, is formed within an aperture formed in silicon oxide films and is interposed between the wiring line and the bonding pad.
摘要翻译： 要防止接合焊盘与接合焊盘之下的绝缘膜之间的剥离。 主要由W构成的层叠膜形成在形成于氧化硅膜中的孔内，其机械强度高于使用Al合金膜作为主导电层的布线层和焊盘，并且插入在布线 和接合垫。
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公开(公告)号：US20060289917A1
公开(公告)日：2006-12-28
申请号：US11473229
申请日：2006-06-23
申请人： Tsuyoshi Fujiwara , Toshinori Imai , Takeshi Saikawa , Yoshihiro Kawasaki , Mitsuhiro Toya , Shunji Mori , Yoshiyuki Okabe
发明人： Tsuyoshi Fujiwara , Toshinori Imai , Takeshi Saikawa , Yoshihiro Kawasaki , Mitsuhiro Toya , Shunji Mori , Yoshiyuki Okabe
IPC分类号： H01L29/94
CPC分类号： H01L28/91 , H01L27/10852 , H01L28/87
摘要： Provided is a technology capable of reducing parasitic capacitance of a capacitor while reducing the space occupied by the capacitor. A stacked structure is obtained by forming, over a capacitor composed of a lower electrode, a capacitor insulating film and an intermediate electrode, another capacitor composed of the intermediate electrode, another capacitor insulating film and an upper electrode. Since the intermediate electrode has a step difference, each of the distance between the intermediate electrode and lower electrode and the distance between the intermediate electrode and upper electrode in a region other than the capacitor formation region becomes greater than that in the capacitor formation region. For example, the lower electrode is brought into direct contact with the capacitor insulating film in the capacitor formation region, while the lower electrode is not brought into direct contact with the capacitor insulating film in the region other than the capacitor formation region.
摘要翻译： 提供了一种能够减小电容器的寄生电容同时减小电容器所占空间的技术。 通过在由下电极构成的电容器，电容绝缘膜和中间电极上形成电容器，由中间电极，另一电容绝缘膜和上电极构成的另一电容器形成堆叠结构。 由于中间电极具有台阶差，所以在电容器形成区域以外的区域中，中间电极和下部电极之间的距离以及中间电极和上部电极之间的距离变得比电容器形成区域的大。 例如，下电极与电容器形成区域中的电容绝缘膜直接接触，而在电容器形成区域以外的区域中，下电极不与电容器绝缘膜直接接触。
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6.发明授权公开(公告)号：US07582901B2
公开(公告)日：2009-09-01
申请号：US11059651
申请日：2005-02-17
申请人： Kenichi Takeda , Tsuyoshi Fujiwara , Toshinori Imai , Tsuyoshi Ishikawa , Toshiyuki Mine , Makoto Miura
发明人： Kenichi Takeda , Tsuyoshi Fujiwara , Toshinori Imai , Tsuyoshi Ishikawa , Toshiyuki Mine , Makoto Miura
IPC分类号： H01L29/76
CPC分类号： H01L28/40 , H01L21/76838
摘要： An MIM capacitor using a high-permittivity dielectric film such as tantalum oxide. The MIM capacitor includes an upper electrode, a dielectric film, and a lower electrode. A second dielectric film and the dielectric film are formed between the upper electrode and the lower electrode, at the end of the MIM capacitor. The second dielectric film is formed to have an opening at the top of the lower electrode. The dielectric film abuts the lower electrode via the opening. The upper electrode is formed on the dielectric film. The upper electrode and the dielectric film are formed in such a manner as to embrace the opening entirely, and the second dielectric film and the lower electrode are formed so that the respective widths are the same as, or greater than, the widths of the upper electrode and the dielectric film.
摘要翻译： 使用诸如氧化钽的高介电常数电介质膜的MIM电容器。 MIM电容器包括上电极，电介质膜和下电极。 在MIM电容器的端部，在上电极和下电极之间形成第二电介质膜和电介质膜。 第二电介质膜形成为在下电极的顶部具有开口。 电介质膜经由开口抵接下电极。 上电极形成在电介质膜上。 上部电极和电介质膜以完全包围开口的方式形成，并且第二电介质膜和下部电极形成为使得各个宽度与上部的宽度相同或更大 电极和电介质膜。
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公开(公告)号：US06982200B2
公开(公告)日：2006-01-03
申请号：US10748286
申请日：2003-12-31
申请人： Junji Noguchi , Toshinori Imai , Tsuyoshi Fujiwara
发明人： Junji Noguchi , Toshinori Imai , Tsuyoshi Fujiwara
IPC分类号： H01L21/8242
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76807 , H01L21/76814 , H01L21/76832 , H01L21/76838 , H01L23/5223 , H01L23/53233 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of manufacturing a semiconductor device which has reliable buried interconnects (wirings) and a reliable MIM capacitor. An interconnect and a capacitor bottom electrode are formed inside a hole made in six insulation films. Then a barrier insulation film is formed on the uppermost film (of the above six insulation films) including the interconnect and the top face of the bottom electrode. After two insulation films are formed above the barrier insulation film, a hole is made in the two insulation films and a capacitor top electrode is buried in that hole. The barrier insulation film also functions as a capacity insulation film for the capacitor. Then, after three other insulation films are formed on the upper film (of the above two insulation films) including the top face of the top electrode, a hole is made in the barrier insulation film, the two insulation films, and the three other insulation films, and another interconnect is buried in that hole.
摘要翻译： 公开了一种具有可靠的埋地互连（布线）和可靠的MIM电容器的半导体器件的制造方法。 在由六个绝缘膜制成的孔内形成互连和电容器底部电极。 然后在包括互连件和底部电极的顶面的最上面的膜（上述六个绝缘膜）上形成阻挡绝缘膜。 在阻挡绝缘膜上方形成两个绝缘膜之后，在两个绝缘膜中形成孔，并且在该孔中埋置电容器顶部电极。 阻挡绝缘膜还用作电容器的电容绝缘膜。 然后，在上电极（上述两个绝缘膜）的上部膜上形成三个绝缘膜之后，在隔离绝缘膜，两个绝缘膜和三个绝缘层中形成一个孔 电影，另一个互连被埋在那个洞里。
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公开(公告)号：US20050212082A1
公开(公告)日：2005-09-29
申请号：US11059651
申请日：2005-02-17
申请人： Kenichi Takeda , Tsuyoshi Fujiwara , Toshinori Imai , Tsuyoshi Ishikawa , Toshiyuki Mine , Makoto Miura
发明人： Kenichi Takeda , Tsuyoshi Fujiwara , Toshinori Imai , Tsuyoshi Ishikawa , Toshiyuki Mine , Makoto Miura
IPC分类号： H01L21/02 , H01L21/768 , H01L27/108
CPC分类号： H01L28/40 , H01L21/76838
摘要： An MIM capacitor using a high-permittivity dielectric film such as tantalum oxide. The MIM capacitor includes an upper electrode, a dielectric film, and a lower electrode. A second dielectric film and the dielectric film are formed between the upper electrode and the lower electrode, at the end of the MIM capacitor. The second dielectric film is formed to have an opening at the top of the lower electrode. The dielectric film abuts the lower electrode via the opening. The upper electrode is formed on the dielectric film. The upper electrode and the dielectric film are formed in such a manner as to embrace the opening entirely, and the second dielectric film and the lower electrode are formed so that the respective widths are the same as, or greater than, the widths of the upper electrode and the dielectric film.
摘要翻译： 使用诸如氧化钽的高介电常数电介质膜的MIM电容器。 MIM电容器包括上电极，电介质膜和下电极。 在MIM电容器的端部，在上电极和下电极之间形成第二电介质膜和电介质膜。 第二电介质膜形成为在下电极的顶部具有开口。 电介质膜经由开口抵接下电极。 上电极形成在电介质膜上。 上部电极和电介质膜以完全包围开口的方式形成，并且第二电介质膜和下部电极形成为使得各个宽度与上部的宽度相同或更大 电极和电介质膜。
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公开(公告)号：US08212649B2
公开(公告)日：2012-07-03
申请号：US13238056
申请日：2011-09-21
IPC分类号： H01C1/12
CPC分类号： H01L23/5228 , H01L27/0688 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to the present invention includes: a lower-surface oxidation preventing insulating film formed on a lower surface of a metal resistor element; an upper-surface oxidation preventing insulating film formed on an upper surface of the metal resistor element; and a side-surface oxidation preventing insulating film formed only near a side surface of the metal resistor element by performing anisotropic etching after being deposited on a whole surface of a wafer in a process separated from the lower-surface oxidation preventing insulating film and the upper-surface oxidation preventing insulating film. According to the present invention, it is possible to prevent the increase of the resistance value due to the oxidation of the metal resistor element and also to prevent the increase of the parasitic capacitance between metal wiring layers without complicating the fabrication process.
摘要翻译： 根据本发明的半导体器件包括：形成在金属电阻器元件的下表面上的下表面的氧化防止绝缘膜; 形成在所述金属电阻元件的上表面上的上表面氧化防止绝缘膜; 以及侧面氧化防止绝缘膜，其仅在金属电阻元件的侧面附近形成，在与下表面的氧化防止绝缘膜分离的工序中沉积在晶片的整个表面上，进行各向异性蚀刻 表面氧化防止绝缘膜。 根据本发明，可以防止由于金属电阻元件的氧化引起的电阻值的增加，并且还可以防止金属布线层之间的寄生电容的增加，而不会使制造工艺复杂化。
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公开(公告)号：US08040214B2
公开(公告)日：2011-10-18
申请号：US12481384
申请日：2009-06-09
IPC分类号： H01C1/12
CPC分类号： H01L23/5228 , H01L27/0688 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to the present invention includes: a lower-surface oxidation preventing insulating film formed on a lower surface of a metal resistor element; an upper-surface oxidation preventing insulating film formed on an upper surface of the metal resistor element; and a side-surface oxidation preventing insulating film formed only near a side surface of the metal resistor element by performing anisotropic etching after being deposited on a whole surface of a wafer in a process separated from the lower-surface oxidation preventing insulating film and the upper-surface oxidation preventing insulating film. According to the present invention, it is possible to prevent the increase of the resistance value due to the oxidation of the metal resistor element and also to prevent the increase of the parasitic capacitance between metal wiring layers without complicating the fabrication process.
摘要翻译： 根据本发明的半导体器件包括：形成在金属电阻器元件的下表面上的下表面的氧化防止绝缘膜; 形成在所述金属电阻元件的上表面上的上表面氧化防止绝缘膜; 以及侧面氧化防止绝缘膜，其仅在金属电阻元件的侧面附近形成，在与下表面的氧化防止绝缘膜分离的工序中沉积在晶片的整个表面上，进行各向异性蚀刻 表面氧化防止绝缘膜。 根据本发明，可以防止由于金属电阻元件的氧化引起的电阻值的增加，并且还可以防止金属布线层之间的寄生电容的增加，而不会使制造工艺复杂化。
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