公开(公告)号：US5864341A

公开(公告)日：1999-01-26

申请号：US761875

申请日：1996-12-06

申请人： Troy Neal Hicks ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

发明人： Troy Neal Hicks ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3891 ,  G06F9/3824 ,  G06F9/3853 ,  G06F9/3885

摘要： The present invention is directed to a method and apparatus for dispatching instructions in an information handling system. A pre-execution queue stores instructions, and at least one execution cluster is operably coupled to the pre-execution queue. An execution cluster comprises an early execution unit for executing a first instruction dispatched from the pre-execution queue to generate and forward a first result and a late execution unit for executing a second instruction dispatched from the pre-execution queue to generate and forward a second result after the first execution unit forwards the first result. The invention further includes circuitry operably associated with the pre-execution queue, and a method for prioritizing the order in which the instructions in the pre-execution queue are dispatched to the execution cluster.

摘要翻译： 本发明涉及一种用于在信息处理系统中调度指令的方法和装置。 预执行队列存储指令，并且至少一个执行群集可操作地耦合到预执行队列。 执行群包括一个早期执行单元，用于执行从预执行队列发出的第一指令，以产生和转发第一结果;以及后期执行单元，用于执行从预执行队列发出的第二指令，以产生和转发第二个 第一执行单元转发第一个结果后的结果。 本发明还包括可操作地与预执行队列相关联的电路，以及用于将预执行队列中的指令分派到执行群集的顺序的优先级的方法。

公开(公告)号：US5860014A

公开(公告)日：1999-01-12

申请号：US729307

申请日：1996-10-15

申请人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

发明人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3861

摘要： A method and apparatus for maintaining content of registers of a processor which uses the registers for processing instructions. Entries are stored in a buffer for restoring register content in response to an interruption by an interruptible instruction. Entries include information for reducing the number of entries selected for the restoring. A set of the buffer entries is selected, in response to the interruption and the information, for restoring register content. The set includes only entries which are necessary for restoring the content in response to the interruption so that the content of the processor registers may be restored in a single processor cycle, even if multiple entries are stored for a first one of the registers and multiple entries are stored for a second one of the registers.

摘要翻译： 一种用于维护使用寄存器处理指令的处理器的寄存器的内容的方法和装置。 条目存储在缓冲器中，用于通过可中断指令中断来恢复寄存器内容。 条目包括用于减少为恢复选择的条目数量的信息。 响应于中断和信息来选择一组缓冲器条目用于恢复寄存器内容。 该集合仅包括为了响应于中断而恢复内容所必需的条目，使得处理器寄存器的内容可以在单个处理器周期中被恢复，即使对于第一个寄存器和多个条目存储了多个条目 存储在第二个寄存器中。

公开(公告)号：US6079002A

公开(公告)日：2000-06-20

申请号：US935573

申请日：1997-09-23

申请人： Larry Edward Thatcher ,  John Stephen Muhich ,  Steven Wayne White ,  Troy Neal Hicks

发明人： Larry Edward Thatcher ,  John Stephen Muhich ,  Steven Wayne White ,  Troy Neal Hicks

IPC分类号： G06F9/38 ,  G06F12/00

CPC分类号： G06F9/3867 ,  G06F9/3824

摘要： A method and system in a data processing system for accessing information using an instruction specifying a memory address is disclosed. The method and system comprises issuing the instruction to an execution unit and storing an address derived from the specified address. The method and system also includes accessing a cache to obtain the information, using the derived address and determining, in response to a signal indicating that there has been a cache miss, if there is a location available to store the specified address in a queue. According to the system and method disclosed herein, the present invention allows for dynamic pipeline expansion of a processor without splitting this function between components depending upon the reason expansion was required, thereby increasing overall system performance.

摘要翻译： 公开了一种使用指定存储器地址的指令访问信息的数据处理系统中的方法和系统。 该方法和系统包括向执行单元发出指令并存储从指定地址导出的地址。 该方法和系统还包括访问高速缓存以获得信息，使用导出的地址并且响应于指示已经存在高速缓存未命中的信号确定是否存在可用于将指定的地址存储在队列中的位置。 根据本文公开的系统和方法，根据需要扩展的原因，本发明允许处理器的动态管道扩展，而不会在组件之间分离该功能，从而提高整体系统性能。

公开(公告)号：US5870582A

公开(公告)日：1999-02-09

申请号：US829671

申请日：1997-03-31

申请人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

发明人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F9/38

CPC分类号： G06F9/3855 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3863

摘要： In a method and apparatus for allocating processor resources in a data processing system, instructions are dispatched and tagged for processing. A processor resource snoops to obtain execution results for the tagged instructions. Such an instruction is logically "finished" in response to determining that it will not cause an interrupt (which includes not changing the sequence of completing instructions), and "completed" in response to finishing all earlier dispatched instructions. Information is entered for such an instructions in rename buffer in response to the instruction targeting an architected register, and such a rename buffer entry is released in response to completing the entry's instruction. The rename buffer may comprise a history buffer. Also, information for the instructions is entered in a completion queue in response to dispatching the instructions, and the queue entry for such an instruction is released in response to completion of the instruction. Also, the instructions are grouped, a group having solely a single interruptible instruction, and further including non-interruptible instructions dispatched following the interruptible instruction. Thus, there may be numerous non-interruptible instructions in such a group. Such an interruptible instruction is logically "finished" in response to determining that it will not cause an interrupt, and "completed" in response to finishing all earlier dispatched instructions. Such a non-interruptible instruction is logically "finished" and "completed" in response to completion of its associated interruptible instruction, so that such a non-interruptible instruction may complete before it is dispatched.

摘要翻译： 在用于在数据处理系统中分配处理器资源的方法和装置中，调度和标记用于处理的指令。 处理器资源被窥探以获得标记指令的执行结果。 响应于确定不会导致中断（其不包括改变完成指令的顺序），并且响应于完成所有先前分派的指令而“完成”，这样的指令在逻辑上“完成”。 响应于针对架构化寄存器的指令，在重命名缓冲器中输入这样的指令的信息，并且响应于完成条目的指令而释放这样的重命名缓冲器条目。 重命名缓冲器可以包括历史缓冲器。 此外，响应于分派指令，将指令的信息输入到完成队列中，并且响应于指令的完成而释放这样的指令的队列条目。 此外，指令被分组，仅具有单个可中断指令的组，并且还包括在可中断指令之后分派的不可中断指令。 因此，在这样的组中可能存在许多不可中断的指令。 这种可中断指令在逻辑上“完成”以响应于确定它不会引起中断，并且响应于完成所有先前分派的指令而“完成”。 响应于其相关联的可中断指令的完成，这种不可中断指令被逻辑地“完成”和“完成”，使得这种不可中断指令可以在其被分派之前完成。

公开(公告)号：US6098167A

公开(公告)日：2000-08-01

申请号：US829667

申请日：1997-03-31

申请人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

发明人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3863

摘要： In maintaining the state of a processor, a dispatched instruction is given an identification tag and an associated entry in an architectural register table. The identification tag of the dispatched instruction is written to the entry in the architectural register table, if the identification tag of the dispatched instruction is more recent than a prior instruction identification tag stored in the entry.

摘要翻译： 在维护处理器的状态时，在架构寄存器表中给出分派指令的识别标签和相关联的条目。 如果调度指令的识别标签比存储在条目中的先前指令标识标签更新，则将调度指令的识别标签写入架构寄存器表中的条目。

公开(公告)号：US5913048A

公开(公告)日：1999-06-15

申请号：US829663

申请日：1997-03-31

申请人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

发明人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F9/38

CPC分类号： G06F9/3855 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3863

摘要： The invention relates to a method for issuing instructions in a processor. In one version of the invention, the method includes the steps of assigning an identification tag to an instruction, and dispatching the instruction, the identification tag and source information to an execution queue.

摘要翻译： 本发明涉及一种在处理器中发出指令的方法。 在本发明的一个版本中，该方法包括以下步骤：向指令分配识别标签，并将指令，识别标签和源信息分派到执行队列。

公开(公告)号：US5887161A

公开(公告)日：1999-03-23

申请号：US829662

申请日：1997-03-31

申请人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

发明人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： The invention relates to a method for issuing instructions in a processor. In one version of the invention, the method includes the steps of dispatching the instruction and source information to a queue, determining validity of the source information, and issuing the instruction for execution in response to the source information validity.

摘要翻译： 本发明涉及一种在处理器中发出指令的方法。 在本发明的一个版本中，该方法包括以下步骤：将指令和源信息发送到队列，确定源信息的有效性，以及响应源信息有效性发出执行指令。

公开(公告)号：US5870612A

公开(公告)日：1999-02-09

申请号：US729309

申请日：1996-10-15

申请人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

发明人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F9/38 ,  G06F9/46

CPC分类号： G06F9/462 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3861

摘要： The invention includes a method and apparatus for maintaining content of predefined registers of a processor which uses the registers for executing instructions, including an interruptible instruction. According to the invention, instructions are dispatched, including instructions ("targeting instructions") which target registers for holding register content, and an interruptible instruction. The content of a register is altered in response to executing a targeting instruction. An entry of register content is stored only for selected ones of the dispatched targeting instructions.

摘要翻译： 本发明包括一种用于维护处理器的预定义寄存器的内容的方法和装置，其使用该寄存器来执行包括可中断指令的指令。 根据本发明，调度指令，包括目标用于保持寄存器内容的寄存器的指令（“目标指令”）和可中断指令。 响应于执行目标指令而改变寄存器的内容。 注册内容的条目仅存储于所选派生的定位指令。

公开(公告)号：US06658534B1

公开(公告)日：2003-12-02

申请号：US09052247

申请日：1998-03-31

申请人： Steven Wayne White ,  Hung Qui Le ,  Kurt Alan Feiste ,  Paul Joseph Jordan

发明人： Steven Wayne White ,  Hung Qui Le ,  Kurt Alan Feiste ,  Paul Joseph Jordan

IPC分类号： G06F1200

CPC分类号： G06F9/382 ,  G06F9/3804 ,  G06F12/0862

摘要： The mechanism to reduce instruction cache miss penalties by initiating an early cache line prefetch is implemented. The mechanism provides for an early prefetch of a next succeeding cache line before an instruction cache miss is detected during a fetch which causes an instruction cache miss. The prefetch is initiated when it is guaranteed that instructions in the subsequent cache line will be referenced. This occurs when the current instruction is either a non-branch instruction, so instructions will execute sequentially, or if the current instruction is a branch instruction, but the branch forward is sufficiently short. If the current instruction is a branch, but the branch forward is to the next sequential cache line, a prefetch of the next sequential cache line may be performed. In this way, cache miss latencies may be reduced without generating cache pollution due to the prefetch of cache lines which are subsequently unreferenced.

摘要翻译： 实现了通过启动早期高速缓存行预取来减少指令高速缓存未达错误的机制。 该机制在提取期间检测到指令高速缓存未命中导致指令高速缓存未命中之前提供对下一个后续高速缓存行的早期预取。 当保证将引用后续高速缓存行中的指令时，启动预取。 当当前指令是非分支指令时，会发生这种情况，因此指令将顺序执行，或者当前指令是分支指令，但分支前进足够短。 如果当前指令是分支，而分支转发到下一个顺序高速缓存行，则可以执行下一个顺序高速缓存行的预取。 以这种方式，可以减少高速缓存未命中延迟，而不会由于先前未被引用的高速缓存线的预取而产生高速缓存污染。

公开(公告)号：US5805849A

公开(公告)日：1998-09-08

申请号：US829592

申请日：1997-03-31

申请人： Paul Joseph Jordan ,  Brian R. Konigsburg ,  Hung Qui Le ,  Steven Wayne White

发明人： Paul Joseph Jordan ,  Brian R. Konigsburg ,  Hung Qui Le ,  Steven Wayne White

IPC分类号： G06F9/38

CPC分类号： G06F9/3855 ,  G06F9/3836 ,  G06F9/3857

摘要： A data processor assigns a unique identifier to each instruction. As there are a finite number of unique identifiers, the identifiers are reused during execution of a program within the data processing system. To maintain an age relationship between instructions executing in the pipeline processor, a methodology is developed to ensure that reused identifiers are properly designated as being younger than their older but larger in magnitude, counterparts. To resolve this issue, assume that the identifier assigned to each instruction has N bits, and therefore, there are 2.sup.N identifiers to be assigned to instructions in the program. The 2.sup.N identifiers are separated into 2.sup.m banks. In addition to assigning identifiers to each instruction, an identifier assignment logic circuit within the pipeline processor provides a global signal that indicates which bank is a youngest bank from which the identifiers are assigned to a remaining portion of the pipeline processor. The global signal preconditions portions of the two identifiers being compared. Subsequently, a result of this conditioning is concatenated with a remaining portion of a selected identifier. The modification of the upper bits of the identifier maintains a relative age position for the identifiers and their associated instructions in the pipelined processor.

摘要翻译： 数据处理器为每个指令分配唯一的标识符。 由于存在有限数量的唯一标识符，所以在数据处理系统内的程序执行期间重新使用标识符。 为了保持在流水线处理器中执行的指令之间的年龄关系，开发了一种方法，以确保重复使用的标识符被正确地指定为年龄小于较大的，较大的数量。 为了解决这个问题，假定分配给每个指令的标识符具有N位，因此，有2N个标识符被分配给程序中的指令。 2N个标识符分成2m个银行。 除了为每个指令分配标识符之外，流水线处理器内的标识符分配逻辑电路提供一个全局信号，其指示哪个存储体是最小的存储体，其中标识符从其被分配给流水线处理器的剩余部分。 两个标识符的全局信号前提条件部分被比较。 随后，这种调理的结果与所选标识符的剩余部分连接。 标识符的高位的修改保持流水线处理器中的标识符及其相关联的指令的相对年龄位置。