公开(公告)号：US20080179758A1

公开(公告)日：2008-07-31

申请号：US11698602

申请日：2007-01-25

申请人： Tse E. Wong ,  Samuel D. Tonomura ,  Stephen E. Sox ,  Timothy E. Dearden ,  Clifton Quan ,  Polwin C. Chan ,  Mark S. Hauhe

发明人： Tse E. Wong ,  Samuel D. Tonomura ,  Stephen E. Sox ,  Timothy E. Dearden ,  Clifton Quan ,  Polwin C. Chan ,  Mark S. Hauhe

IPC分类号： H01L23/538 ,  H01L27/14 ,  H01L21/70

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A stacked integrated circuit assembly includes a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC is disposed between the substrate and the SFIC. The stacked integrated circuit assembly includes least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.

摘要翻译： 堆叠集成电路组件包括具有至少一个衬底连接焊盘的顶表面的衬底。 第一倒装芯片集成电路（FFIC）设置在基板上方，第二倒装芯片集成电路（SFIC）设置在FFIC上方。 FFIC设置在基板和SFIC之间。 堆叠集成电路组件包括衬底连接焊盘和FFIC之间的至少一个焊接连接以及FFIC和SFIC之间的至少一个焊接连接。

公开(公告)号：US07888176B2

公开(公告)日：2011-02-15

申请号：US12557205

申请日：2009-09-10

申请人： Tse E. Wong ,  Samuel D. Tonomura ,  Stephen E. Sox ,  Timothy E. Dearden ,  Clifton Quan ,  Polwin C. Chan ,  Mark S. Hauhe

发明人： Tse E. Wong ,  Samuel D. Tonomura ,  Stephen E. Sox ,  Timothy E. Dearden ,  Clifton Quan ,  Polwin C. Chan ,  Mark S. Hauhe

IPC分类号： H01L21/00

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： In one or more embodiments, a method of producing a stacked integrated circuit assembly includes providing a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC may be disposed between the substrate and the SFIC. The method includes making at least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.

摘要翻译： 在一个或多个实施例中，一种制造堆叠集成电路组件的方法包括提供具有至少一个衬底连接焊盘的顶表面的衬底。 第一倒装芯片集成电路（FFIC）设置在基板上方，第二倒装芯片集成电路（SFIC）设置在FFIC上方。 FFIC可以设置在基板和SFIC之间。 该方法包括在衬底连接焊盘和FFIC之间进行至少一个焊接连接以及FFIC和SFIC之间的至少一个焊接连接。

公开(公告)号：US07605477B2

公开(公告)日：2009-10-20

申请号：US11698602

申请日：2007-01-25

申请人： Tse E. Wong ,  Samuel D. Tonomura ,  Stephen E. Sox ,  Timothy E. Dearden ,  Clifton Quan ,  Polwin C. Chan ,  Mark S. Hauhe

发明人： Tse E. Wong ,  Samuel D. Tonomura ,  Stephen E. Sox ,  Timothy E. Dearden ,  Clifton Quan ,  Polwin C. Chan ,  Mark S. Hauhe

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A stacked integrated circuit assembly includes a substrate having a top surface with at least one substrate connection pad. A first flip chip integrated circuit (FFIC) is disposed above the substrate, and a second flip chip integrated circuit (SFIC) is disposed above the FFIC. The FFIC is disposed between the substrate and the SFIC. The stacked integrated circuit assembly includes least one solder connection between the substrate connection pad and the FFIC and at least one solder connection between the FFIC and the SFIC.

摘要翻译： 堆叠集成电路组件包括具有至少一个衬底连接焊盘的顶表面的衬底。 第一倒装芯片集成电路（FFIC）设置在基板上方，第二倒装芯片集成电路（SFIC）设置在FFIC上方。 FFIC设置在基板和SFIC之间。 堆叠集成电路组件包括衬底连接焊盘和FFIC之间的至少一个焊接连接以及FFIC和SFIC之间的至少一个焊接连接。