公开(公告)号：US5742804A

公开(公告)日：1998-04-21

申请号：US685607

申请日：1996-07-24

申请人： Tse-Yu Yeh ,  Mircea Poplingher ,  Kent G. Fielden ,  Hans Mulder ,  Rajiv Gupta ,  Dale Morris ,  Michael Schlansker

发明人： Tse-Yu Yeh ,  Mircea Poplingher ,  Kent G. Fielden ,  Hans Mulder ,  Rajiv Gupta ,  Dale Morris ,  Michael Schlansker

IPC分类号： G06F9/38

CPC分类号： G06F9/3804 ,  G06F9/3836 ,  G06F9/3846

摘要： A processor and method that reduces instruction fetch penalty in the execution of a program sequence of instructions comprises a branch predict instruction that is inserted into the program at a location which precedes the branch. The branch predict instruction has an opcode that specifies a branch as likely to be taken or not taken, and which also specifies a target address of the branch. A block of target instructions, starting at the target address, is prefetched into the instruction cache of the processor so that the instructions are available for execution prior to the point in the program where the branch is encountered. Also specified by the opcode is an indication of the size of the block of target instructions, and a trace vector of a path in the program sequence that leads to the target from the branch predict instruction for better utilization of limited memory bandwidth.

摘要翻译： 在程序指令序列的执行中减少指令提取损失的处理器和方法包括在分支之前的位置处插入到程序中的分支预测指令。 分支预测指令具有指定可能被采用或未被采用的分支的操作​​码，并且还指定分支的目标地址。 从目标地址开始的目标指令块被预取到处理器的指令高速缓存中，使得指令在程序中遇到分支的点之前可用于执行。 操作码还指定了目标指令块的大小的指示，以及由分支预测指令导致目标的程序序列中的路径的跟踪向量，以更好地利用有限的存储器带宽。

公开(公告)号：US06611910B2

公开(公告)日：2003-08-26

申请号：US09169868

申请日：1998-10-12

申请人： Harshvardhan Sharangpani ,  Tse-Yu Yeh ,  Michael Paul Corwin ,  Millind Mittal ,  Kent G. Fielden ,  Dale Morris ,  Rajiv Gupta ,  Michael Schlansker ,  Mircea Poplingher

发明人： Harshvardhan Sharangpani ,  Tse-Yu Yeh ,  Michael Paul Corwin ,  Millind Mittal ,  Kent G. Fielden ,  Dale Morris ,  Rajiv Gupta ,  Michael Schlansker ,  Mircea Poplingher

IPC分类号： G06F930

CPC分类号： G06F9/3806 ,  G06F9/322 ,  G06F9/325 ,  G06F9/3844 ,  G06F9/3846

摘要： A branch operation is processed using a branch predict instruction and an associated branch instruction. The branch predict instruction indicates a predicted direction, a target address, and an instruction address for the associated branch instruction. When the branch predict instruction is detected, the target address is stored at an entry indicated by the associated branch instruction address and a prefetch request is triggered to the target address. The branch predict instruction may also include hint information for managing the storage and use of the branch prediction information.

摘要翻译： 使用分支预测指令和相关联的分支指令来处理分支操作。 分支预测指示指示相关联的分支指令的预测方向，目标地址和指令地址。 当检测到分支预测指令时，目标地址被存储在由关联的分支指令地址指示的条目上，并且预取请求被触发到目标地址。 分支预测指令还可以包括用于管理分支预测信息的存储和使用的提示信息。

公开(公告)号：US06742108B1

公开(公告)日：2004-05-25

申请号：US09152751

申请日：1998-09-14

申请人： Kent G. Fielden

发明人： Kent G. Fielden

IPC分类号： G06F1500

CPC分类号： G06F9/3865 ,  G06F9/30043 ,  G06F9/3842

摘要： A load is executed speculatively as a dismissible load instruction, which does not take exceptions, and a check instruction, which is in the same format as the dismissible load, that when executed determines whether an exception should be taken on the dismissible load. In this manner, a load may be executed speculatively while ensuring that an exception occurs at the same time it would have occurred had the load been executed non-speculatively.

摘要翻译： 负载被推测性地作为不允许的负载指令执行，其不具有例外情况，以及与可被允许的负载格式相同的检查指令，当执行时，确定是否在可容许的负载上采用例外。 以这种方式，可以推测性地执行负载，同时确保在非推测性地执行了负载的同时发生异常。

公开(公告)号：US5802337A

公开(公告)日：1998-09-01

申请号：US890182

申请日：1997-07-09

申请人： Kent G. Fielden

发明人： Kent G. Fielden

IPC分类号： G06F9/312 ,  G06F9/38

CPC分类号： G06F9/3865 ,  G06F9/30043 ,  G06F9/3842

摘要： A load is executed speculatively as a dismissible load instruction, which does not take exceptions, and a check instruction, which is in the same format as the dismissible load, that when executed determines whether an exception should be taken on the dismissible load. In this manner, a load may be executed speculatively while ensuring that an exception occurs at the same time it would have occurred had the load been executed non-speculatively.

摘要翻译： 负载被推测性地作为不允许的负载指令执行，其不具有例外情况，以及与可被允许的负载格式相同的检查指令，当执行时，确定是否在可容许的负载上采用例外。 以这种方式，可以推测性地执行负载，同时确保在非推测性地执行了负载的同时发生异常。

公开(公告)号：US5699537A

公开(公告)日：1997-12-16

申请号：US577865

申请日：1995-12-22

申请人： Harshvardhan P. Sharangpani ,  Kent G. Fielden ,  Hans J. Mulder

发明人： Harshvardhan P. Sharangpani ,  Kent G. Fielden ,  Hans J. Mulder

IPC分类号： G06F9/38

CPC分类号： G06F9/3891 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

摘要： A processor microarchitecture for efficient dynamic instruction scheduling and execution. The invention includes a predetermined number of independent dispatch queues. The invention also includes a cluster of execution units coupled to each dispatch queue such that the dispatch queue and the corresponding cluster of execution units forms an independent micropipeline. Chain-building and steering logic coupled to the dispatch queues identifies a consumer instruction relying on a producer instruction for an operand, and issues the consumer instruction to the same dispatch queue as the producer instruction that it is dependent upon. The instructions are issued from the dispatch queue to the corresponding cluster of execution units. In one embodiment, the output of each execution unit in the cluster is routed to the inputs of all execution units in the cluster such that the result of executing the producer instruction is readily available as an operand for execution of the consumer instruction.

摘要翻译： 用于高效动态指令调度和执行的处理器微架构。 本发明包括预定数量的独立调度队列。 本发明还包括耦合到每个调度队列的执行单元的集群，使得调度队列和相应的执行单元簇形成独立的微管线。 耦合到调度队列的链建立和转向逻辑根据操作数的生产者指令识别消费者指令，并将消费者指令发布到与其依赖的生产者指令相同的调度队列。 指令从调度队列发出到相应的执行单元集群。 在一个实施例中，群集中的每个执行单元的输出被路由到群集中的所有执行单元的输入，使得执行生成器指令的结果容易作为用于执行消费者指令的操作数。