公开(公告)号：US07849327B2

公开(公告)日：2010-12-07

申请号：US11040261

申请日：2005-01-19

申请人： Hin L. Leung ,  Kushagra V. Vaid ,  Amy L. Santoni ,  Dale Morris ,  Jonathan Ross

发明人： Hin L. Leung ,  Kushagra V. Vaid ,  Amy L. Santoni ,  Dale Morris ,  Jonathan Ross

IPC分类号： G06F11/30 ,  G06F12/14

CPC分类号： G06F9/4812 ,  G06F9/45558 ,  G06F2009/45579

摘要： A technique to improve the performance of virtualized input/output (I/O) resources of a microprocessor within a virtual machine environment. More specifically, embodiments of the invention enable accesses of virtualized I/O resources to be made by guest software without necessarily invoking host software. Furthermore, embodiments of the invention enable more efficient delivery of interrupts to guest software by alleviating the need for host software to be invoked in the delivery process.

摘要翻译： 一种提高虚拟机环境中微处理器的虚拟化输入/输出（I / O）资源的性能的技术。 更具体地，本发明的实施例使得能够由客户软件访问虚拟化I / O资源，而不必调用主机软件。 此外，本发明的实施例通过减轻在传送过程中调用主机软件的需要，可以更有效地将中断传送给客户软件。

公开(公告)号：US07523455B2

公开(公告)日：2009-04-21

申请号：US10139074

申请日：2002-05-03

申请人： Dale Morris

发明人： Dale Morris

IPC分类号： G06F9/46

CPC分类号： G06F9/461 ,  G06F9/3851

摘要： A method for application managed CPU context switching. The method includes determining whether state data of a CPU is valid for a process. The determining is performed by the process itself. If the state data of the CPU is not valid for the process, the process accesses functional hardware of the CPU to load new state data into the CPU. The process then continues to execute on the CPU using the new state data. If a context switch occurs, the existing state data of the CPU is invalidated. The state data of the CPU can be invalidated by an operating system without storing the state data in main memory.

摘要翻译： 一种应用程序管理CPU上下文切换的方法。 该方法包括确定CPU的状态数据是否对于进程有效。 该确定由该过程本身执行。 如果CPU的状态数据对于该过程无效，则该进程访问CPU的功能硬件以将新的状态数据加载到CPU中。 然后，该过程将继续使用新的状态数据在CPU上执行。 如果发生上下文切换，则CPU的现有状态数据无效。 CPU的状态数据可以由操作系统无效，而不将状态数据存储在主存储器中。

公开(公告)号：US07441104B2

公开(公告)日：2008-10-21

申请号：US10112783

申请日：2002-03-30

申请人： Dale Morris

发明人： Dale Morris

IPC分类号： G06F9/315 ,  G06F15/00

CPC分类号： G06F9/30021 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/325

摘要： The present invention provides for parallel subword instructions that cause results to be non-contiguously stored in a result register. For example, a targeting-type instruction can specify (implicitly or explicitly) a bit position and the result of each of the parallel subword compare operations can be stored at that bit position within the respective subword location of a result register. Alternatively, for a shifting-type instruction, pre-existing contents of a result register can be shifted one bit toward greater significance while the results are of the present operation are stored in the least-significant bits of respective result-register subword locations. This approach provides the results of multiple parallel subword compare instructions to be combined with relatively few instructions and reduces the maximum lateral movement of information—both of which can enhance performance.

摘要翻译： 本发明提供了使结果非连续地存储在结果寄存器中的并行子字指令。 例如，定向型指令可以指定（隐式地或显式地）位位置，并且每个并行子字比较操作的结果可以被存储在结果寄存器的相应子字位置内的该位位置处。 或者，对于移位型指令，结果寄存器的预先存在的内容可以向着更大的有效位移一位，而将当前操作的结果存储在各个结果寄存器子字位置的最低有效位中。 这种方法提供了多个并行子词比较指令的结果，与相对较少的指令相结合，并减少信息的最大横向移动 - 这两者都可以提高性能。

公开(公告)号：US07421689B2

公开(公告)日：2008-09-02

申请号：US10695267

申请日：2003-10-28

申请人： Jonathan K. Ross ,  Dale Morris ,  Donald C. Soltis, Jr. ,  Rohit Bhatia ,  Eric Delano

发明人： Jonathan K. Ross ,  Dale Morris ,  Donald C. Soltis, Jr. ,  Rohit Bhatia ,  Eric Delano

IPC分类号： G06F9/455

CPC分类号： G06F9/45533

摘要： Virtual-machine-monitor operation and implementation is facilitated by number of easily implemented features and extensions added to the features of a processor architecture. These features, one or more of which are used in various embodiments of the present invention, include a vmsw instruction that provides a means for transitioning between virtualization mode and non-virtualization mode without an interruption, a virtualization fault that faults on an attempt by a priority-0 routine in virtualization mode attempting to execute a privileged instruction, and a flexible highest-implemented-address mechanism to partition virtual address space into a virtualization address space and a non-virtualization address space.

摘要翻译： 虚拟机监视器的操作和实现通过添加到处理器架构的特征中的容易实现的特征和扩展的数量来实现。 这些特征，其中一个或多个在本发明的各种实施例中使用，包括提供用于在不中断的情况下在虚拟化模式和非虚拟化模式之间转换的手段的vmsw指令，虚拟化故障， 尝试执行特权指令的虚拟化模式中的优先级0例程，以及将虚拟地址空间划分为虚拟化地址空间和非虚拟化地址空间的灵活的最高实现地址机制。

公开(公告)号：US20060026360A1

公开(公告)日：2006-02-02

申请号：US10909057

申请日：2004-07-30

申请人： Dale Morris ,  Robert Schreiber

发明人： Dale Morris ,  Robert Schreiber

IPC分类号： G06F12/00 ,  G06F13/28

CPC分类号： G06F12/0804 ,  G06F12/0891

摘要： The present invention provides a system with a cache that indicates which, if any, of its sections contain data having spent status. The invention also provides a method for identifying cache sections containing data having spent status and then purging without writing back to main memory a cache line having at least one section containing data having spent status. The invention further provides a program that specifies a cache-line section containing data that is to acquire “spent” status. “Spent” data, herein, is useless modified or unmodified data that was formerly at least potentially useful data when it was written to a cache. “Purging” encompasses both invalidating and overwriting.

摘要翻译： 本发明提供一种具有高速缓存的系统，其指示其部分（如果有的话）包含具有已用状态的数据。 本发明还提供了一种用于识别包含具有已用状态的数据的缓存部分的方法，然后在不向主存储器写入具有至少一个包含具有已用状态的数据的部分的高速缓存行的情况下进行清除。 本发明还提供一种程序，其指定包含要获取“已用”状态的数据的高速缓存线段。 这里的“耗费”数据是无用的修改或未修改的数据，以前在写入高速缓存时至少是潜在的有用数据。 “清除”包括无效和覆盖。

公开(公告)号：US06986131B2

公开(公告)日：2006-01-10

申请号：US10175375

申请日：2002-06-18

申请人： Carol L. Thompson ,  Uma Srinivasan ,  Richard E. Hank ,  Dale Morris

发明人： Carol L. Thompson ,  Uma Srinivasan ,  Richard E. Hank ,  Dale Morris

IPC分类号： G06F9/45

CPC分类号： G06F9/325 ,  G06F8/4452 ,  G06F9/30072 ,  G06F9/3842

摘要： A method of efficient code generation for modulo scheduled uncounted loops includes: assigning a given stage predicate to each instruction in each stage, including assigning a given stage predicate to each instruction in each speculative stage; and using the stage predicate to conditionally enable or disable the execution of an instruction during the prologue and epilogue execution.

公开(公告)号：US06931515B2

公开(公告)日：2005-08-16

申请号：US10208095

申请日：2002-07-29

申请人： Jonathan K. Ross ,  Dale Morris

发明人： Jonathan K. Ross ,  Dale Morris

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/312

CPC分类号： G06F9/3865 ,  G06F9/383 ,  G06F9/3842

摘要： A method and system for determining, at run-time, whether or not to defer an exception that arises during execution of a control-speculative load instruction based on a recent history of execution of that control-speculative load instruction. The method and system relies on recent execution history stored in a speculative-load-accelerated-deferral table. If an exception arises during execution of a control-speculative load instruction, then the speculative-load-accelerated-deferral table is searched for an entry corresponding to the control-speculative load instruction. If an entry is found, then the exception is deferred, since the speculative-load-accelerated-deferral table indicates that a recent exception arising from execution of the control-speculative load instruction was not recovered via a chk.s-mediated branch to a recovery block, and not otherwise used by a non-speculative instruction. By contrast, if no entry corresponding to the control-speculative load instruction is found in the speculative-load-accelerated-deferral table, then the exception is immediately handled.

摘要翻译： 一种方法和系统，用于在运行时确定是否推迟在执行控制推测加载指令期间出现的异常，这是基于该控制推测加载指令的执行的最近历史。 该方法和系统依赖于存储在推测加载延迟表中的最近执行历史。 如果在执行控制推测加载指令期间出现异常，则搜索推测加载加速延迟表以查找与控制推测加载指令相对应的条目。 如果找到条目，则异常被延迟，因为推测加载加速延迟表指示由控制推测加载指令的执行引起的最近异常没有通过chk.s介入的分支恢复到 恢复块，而不是由非推测性指令使用。 相反，如果在推测加载延迟表中没有找到与控制推测加载指令相对应的条目，则立即处理异常。

公开(公告)号：US20050091652A1

公开(公告)日：2005-04-28

申请号：US10695267

申请日：2003-10-28

申请人： Jonathan Ross ,  Dale Morris ,  Donald Soltis ,  Rohit Bhatia ,  Eric Delano

发明人： Jonathan Ross ,  Dale Morris ,  Donald Soltis ,  Rohit Bhatia ,  Eric Delano

IPC分类号： G06F9/455

CPC分类号： G06F9/45533

摘要： Virtual-machine-monitor operation and implementation is facilitated by number of easily implemented features and extensions added to the features of a processor architecture. These features, one or more of which are used in various embodiments of the present invention, include a vmsw instruction that provides a means for transitioning between virtualization mode and non-virtualization mode without an interruption, a virtualization fault that faults on an attempt by a priority-0 routine in virtualization mode attempting to execute a privileged instruction, and a flexible highest-implemented-address mechanism to partition virtual address space into a virtualization address space and a non-virtualization address space.

摘要翻译： 虚拟机监视器的操作和实现通过添加到处理器架构的特征中的容易实现的特征和扩展的数量来实现。 这些特征，其中一个或多个在本发明的各种实施例中使用，包括提供用于在不中断的情况下在虚拟化模式和非虚拟化模式之间转换的手段的vmsw指令，虚拟化故障， 尝试执行特权指令的虚拟化模式中的优先级0例程，以及将虚拟地址空间划分为虚拟化地址空间和非虚拟化地址空间的灵活的最高实现地址机制。

公开(公告)号：US20050066153A1

公开(公告)日：2005-03-24

申请号：US10461782

申请日：2003-06-12

申请人： Harshvardhan Sharangpani ,  Tse-Yu Yeh ,  Michael Paul Corwin ,  Millind Mittal ,  Kent Fielden ,  Dale Morris ,  Rajiv Gupta ,  Michael Schlansker ,  Mircea Poplingher

发明人： Harshvardhan Sharangpani ,  Tse-Yu Yeh ,  Michael Paul Corwin ,  Millind Mittal ,  Kent Fielden ,  Dale Morris ,  Rajiv Gupta ,  Michael Schlansker ,  Mircea Poplingher

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC分类号： G06F9/3806 ,  G06F9/322 ,  G06F9/325 ,  G06F9/3844 ,  G06F9/3846

摘要： A branch operation is processed using a branch predict instruction and an associated branch instruction. The branch predict instruction indicates a predicted direction, a target address, and an instruction address for the associated branch instruction. When the branch predict instruction is detected, the target address is stored at an entry indicated by the associated branch instruction address and a prefetch request is triggered to the target address. The branch predict instruction may also include hint information for managing the storage and use of the branch prediction information.

摘要翻译： 使用分支预测指令和相关联的分支指令来处理分支操作。 分支预测指示指示相关联的分支指令的预测方向，目标地址和指令地址。 当检测到分支预测指令时，目标地址被存储在由关联的分支指令地址指示的条目上，并且预取请求被触发到目标地址。 分支预测指令还可以包括用于管理分支预测信息的存储和使用的提示信息。

公开(公告)号：US09146738B2

公开(公告)日：2015-09-29

申请号：US12254687

申请日：2008-10-20

申请人： Dale Morris

发明人： Dale Morris

IPC分类号： G06F9/30

CPC分类号： G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109

摘要： The present invention provides for parallel subword instructions that cause results to be non-contiguously stored in a result register. For example, a targeting-type instruction can specify (implicitly or explicitly) a bit position and the result of each of the parallel subword compare operations can be stored at that bit position within the respective subword location of a result register. Alternatively, for a shifting-type instruction, pre-existing contents of a result register can be shifted one bit toward greater significance while the results are of the present operation are stored in the least-significant bits of respective result-register subword locations. This approach provides the results of multiple parallel subword compare instructions to be combined with relatively few instructions and reduces the maximum lateral movement of information—both of which can enhance performance.

摘要翻译： 本发明提供了使结果非连续地存储在结果寄存器中的并行子字指令。 例如，定向型指令可以指定（隐式地或显式地）位位置，并且每个并行子字比较操作的结果可以被存储在结果寄存器的相应子字位置内的该位位置处。 或者，对于移位型指令，结果寄存器的预先存在的内容可以向着更大的有效位移一位，而将当前操作的结果存储在各个结果寄存器子字位置的最低有效位中。 这种方法提供了多个并行子词比较指令的结果，与相对较少的指令相结合，并减少信息的最大横向移动 - 这两者都可以提高性能。