Circuit structure and driving method thereof, neural network

    公开(公告)号:US11468300B2

    公开(公告)日:2022-10-11

    申请号:US16071985

    申请日:2017-11-14

    Abstract: A circuit structure and a driving method thereof, a neural network are disclosed. The circuit structure includes at least one circuit unit, each circuit unit includes a first group of resistive switching devices and a second group of resistive switching devices, the first group of resistive switching devices includes a resistance gradual-change device, the second group of resistive switching devices includes a resistance abrupt-change device, the first group of resistive switching devices and the second group of resistive switching devices are connected in series, in a case that no voltage is applied, a resistance value of the first group of resistive switching devices is larger than a resistance value of the second group of resistive switching devices.

    Resistive random access memory and manufacturing method thereof

    公开(公告)号:US11355704B2

    公开(公告)日:2022-06-07

    申请号:US17037039

    申请日:2020-09-29

    Abstract: A resistive random access memory and a manufacture method thereof are provided. The resistive random access memory includes: a first electrode, a second electrode, a resistive layer between the first electrode and the second electrode, and at least one thermal enhanced layer; the thermal enhanced layer is adjacent to the resistive layer, and a thermal conductivity of the thermal enhanced layer is less than a thermal conductivity of the first electrode and a thermal conductivity of the second electrode.

    Circuit Structure and Driving Method Thereof, Chip and Authentication Method Thereof, and Electronic Device

    公开(公告)号:US20190088325A1

    公开(公告)日:2019-03-21

    申请号:US16132931

    申请日:2018-09-17

    Abstract: A circuit structure for implementing a physical unclonable function and a driving method thereof, an integrated circuit chip and an authentication method thereof, an electronic device are disclosed. The circuit structure includes: a multilayer circuit, a first address circuit and an output circuit, the multilayer circuit includes a first RRAM device array which is addressable and a second RRAM device array which is addressable; the first address circuit is configured to map a resistance value of a second RRAM device in the second RRAM device array to a first address; the first address is used for positioning a selected first RRAM device; and the output circuit is configured to acquire and process a resistance value of the selected first RRAM device and output a processing result.

    NEURAL NETWORK AND ITS INFORMATION PROCESSING METHOD, INFORMATION PROCESSING SYSTEM

    公开(公告)号:US20210049448A1

    公开(公告)日:2021-02-18

    申请号:US16964435

    申请日:2018-02-24

    Abstract: A neural network and its information processing method, information processing system. The neural network includes N layers of neuron layers connected to each other one by one, except for a first layer of neuron layer, each of the neurons of the other neuron layers includes m dendritic units and one hippocampal unit; the dendritic unit includes a resistance value graded device, the hippocampal unit includes a resistance value mutation device, and the m dendritic units can be provided with different threshold voltage or current, respectively; and the neurons on the nth layer neuron layer are connected to the m dendritic units of the neurons on the n+1th layer neuron layer; wherein N is an integer larger than 3, m is an integer larger than 1, n is an integer larger than 1 and less than N.

    RESISTIVE RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF

    公开(公告)号:US20210028358A1

    公开(公告)日:2021-01-28

    申请号:US17037039

    申请日:2020-09-29

    Abstract: A resistive random access memory and a manufacture method thereof are provided. The resistive random access memory includes: a first electrode, a second electrode, a resistive layer between the first electrode and the second electrode, and at least one thermal enhanced layer; the thermal enhanced layer is adjacent to the resistive layer, and a thermal conductivity of the thermal enhanced layer is less than a thermal conductivity of the first electrode and a thermal conductivity of the second electrode.

    SIGNAL PROCESSING DEVICE AND SIGNAL PROCESSING METHOD

    公开(公告)号:US20200237311A1

    公开(公告)日:2020-07-30

    申请号:US16751110

    申请日:2020-01-23

    Abstract: A signal processing device and a signal processing method. The signal processing device includes a receiver, a memristor array and a classifier. The receiver is configured to receive a first signal. The memristor array includes a plurality of memristor units, each of the plurality of memristor units includes a memristor, and the memristor array is configured to apply the first signal that has been received to at least one memristor unit of the plurality of memristor units and output a second signal based on a memristor resistance value distribution of the memristor array. The classifier is configured to classify the second signal outputted from the memristor array to obtain a type of the first signal.

    Operation method of resistive random access memory and resistive random access memory device

    公开(公告)号:US10475512B2

    公开(公告)日:2019-11-12

    申请号:US15776520

    申请日:2016-12-22

    Abstract: An operation method of a resistance random access memory and a resistance random access memory apparatus are provided. The method includes: applying an initial reset voltage to a storage unit; carrying out a read check operation to acquire a resistance value of the storage unit; judging whether the resistance value of the storage unit reaches a preset target resistance value in a high resistance state; if the resistance value of the storage unit is less than the preset target resistance value in the high resistance state, applying a set voltage to the storage unit to set the storage unit to a preset target resistance value in a low resistance state, then applying a reset voltage of which an amount is increased to the storage unit, and repeating the read check operation and the subsequent steps until the storage unit reaches the preset target resistance value in the high resistance state.

    Circuit structure and driving method thereof, chip and authentication method thereof, and electronic device

    公开(公告)号:US10468099B2

    公开(公告)日:2019-11-05

    申请号:US16132931

    申请日:2018-09-17

    Abstract: A circuit structure for implementing a physical unclonable function and a driving method thereof, an integrated circuit chip and an authentication method thereof, an electronic device are disclosed. The circuit structure includes: a multilayer circuit, a first address circuit and an output circuit, the multilayer circuit includes a first RRAM device array which is addressable and a second RRAM device array which is addressable; the first address circuit is configured to map a resistance value of a second RRAM device in the second RRAM device array to a first address; the first address is used for positioning a selected first RRAM device; and the output circuit is configured to acquire and process a resistance value of the selected first RRAM device and output a processing result.

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