SIGNAL PROCESSING DEVICE AND SIGNAL PROCESSING METHOD

    公开(公告)号:US20200237311A1

    公开(公告)日:2020-07-30

    申请号:US16751110

    申请日:2020-01-23

    Abstract: A signal processing device and a signal processing method. The signal processing device includes a receiver, a memristor array and a classifier. The receiver is configured to receive a first signal. The memristor array includes a plurality of memristor units, each of the plurality of memristor units includes a memristor, and the memristor array is configured to apply the first signal that has been received to at least one memristor unit of the plurality of memristor units and output a second signal based on a memristor resistance value distribution of the memristor array. The classifier is configured to classify the second signal outputted from the memristor array to obtain a type of the first signal.

    Memristor and preparation method thereof

    公开(公告)号:US12133478B2

    公开(公告)日:2024-10-29

    申请号:US17477119

    申请日:2021-09-16

    Abstract: A memristor and a preparation method thereof are provided. The memristor includes at least one memristive unit, each of the at least one memristive unit includes a transistor and at least one memristive component, the transistor includes a source electrode and a drain electrode; and each of the at least one memristive component includes a first electrode, a resistive layer, a second electrode, and a passivation layer, the first electrode is electrically connected with the source electrode or the drain electrode; the resistive layer is provided between the first electrode and the second electrode; and the passivation layer at least covers a sidewall of the resistive layer.

    Nanowire transistor and manufacturing method thereof

    公开(公告)号:US11594623B2

    公开(公告)日:2023-02-28

    申请号:US17058211

    申请日:2018-08-03

    Abstract: A nanowire transistor and a manufacture method thereof are provided. The nanowire transistor includes a semiconductor wire, a semiconductor layer, a source electrode and a drain electrode. The semiconductor wire includes a first semiconductor material and includes a source region, a drain region, and a channel region, along an axial direction of the semiconductor wire, the channel region is between the source region and the drain region; the semiconductor layer includes a second semiconductor material and covers the channel region of the semiconductor wire; the source electrode is in the source region of the semiconductor wire and is in direct contact with the source region of the semiconductor wire, and the drain electrode is in the drain region of the semiconductor wire and is in direct contact with the drain region of the semiconductor wire.

    Circuit structure and driving method thereof, neural network

    公开(公告)号:US11468300B2

    公开(公告)日:2022-10-11

    申请号:US16071985

    申请日:2017-11-14

    Abstract: A circuit structure and a driving method thereof, a neural network are disclosed. The circuit structure includes at least one circuit unit, each circuit unit includes a first group of resistive switching devices and a second group of resistive switching devices, the first group of resistive switching devices includes a resistance gradual-change device, the second group of resistive switching devices includes a resistance abrupt-change device, the first group of resistive switching devices and the second group of resistive switching devices are connected in series, in a case that no voltage is applied, a resistance value of the first group of resistive switching devices is larger than a resistance value of the second group of resistive switching devices.

    Neural network and its information processing method, information processing system

    公开(公告)号:US12217164B2

    公开(公告)日:2025-02-04

    申请号:US16964435

    申请日:2018-02-24

    Abstract: A neural network and its information processing method, information processing system. The neural network includes N layers of neuron layers connected to each other one by one, except for a first layer of neuron layer, each of the neurons of the other neuron layers includes m dendritic units and one hippocampal unit; the dendritic unit includes a resistance value graded device, the hippocampal unit includes a resistance value mutation device, and the m dendritic units can be provided with different threshold voltage or current, respectively; and the neurons on the nth layer neuron layer are connected to the m dendritic units of the neurons on the n+1th layer neuron layer; wherein N is an integer larger than 3, m is an integer larger than 1, n is an integer larger than 1 and less than N.

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