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    Data processing system with an enhanced pipeline control
    1.
    发明授权
    Data processing system with an enhanced pipeline control 失效
    数据处理系统具有增强的流水线控制

    公开(公告)号：US4251859A

    公开(公告)日：1981-02-17

    申请号：US957688

    申请日：1978-11-06

    申请人： Tsugio Momose ,  Akira Fujita ,  Kanji Kubo

    发明人： Tsugio Momose ,  Akira Fujita ,  Kanji Kubo

    IPC分类号： G06F9/28 ,  G06F9/22 ,  G06F9/38

    CPC分类号： G06F9/3836

    摘要： A data processing system, for executing each instruction, by carrying out a plurality of successive partial processing operations, begins to process the first partial processing operation of an instruction succeeding a defeat overlap instruction before execution of the defeat overlap instruction is finished in response to the detection that a predetermined number of machine cycles is further required for the complete execution of the defeat overlap instruction.

    摘要翻译： 用于通过执行多个连续的部分处理操作来执行每个指令的数据处理系统开始处理在执行失败重叠指令之前的失败重叠指令之后的指令的第一部分处理操作，以响应于 检测到完全执行失败重叠指令还需要预定数量的机器周期。

    Apparatus for invalidating the content of an instruction buffer by program store compare check
    2.
    发明授权
    Apparatus for invalidating the content of an instruction buffer by program store compare check 失效
    用于通过程序存储比较检查使指令缓冲器的内容无效的装置

    公开(公告)号：US4500959A

    公开(公告)日：1985-02-19

    申请号：US375587

    申请日：1982-05-06

    申请人： Kanji Kubo ,  Tsugio Momose ,  Chikahiko Izumi

    发明人： Kanji Kubo ,  Tsugio Momose ,  Chikahiko Izumi

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3812

    摘要： In a data processing system having an instruction buffer, inconsistency between an instruction stored in a main memory and the same instruction present in the instruction buffer occurs at the time of a store operation to the memory if the instruction supplied to the store area of the main memory previously has been prefetched to and is present in the instruction buffer. The changing in the memory of the content of the instruction prefetched to the instruction buffer and the fact that the changed instruction is about to be executed are detected on the basis of the instruction fetch address of an instruction to be fetched from the memory to the instruction buffer, the instruction address of the next instruction to be executed, information concerning the byte position at which the instruction to be executed is stored, the store address at which the changed instruction is stored in the main storage and information concerning the byte position in the main storage of the instruction which is changed by the store operation. When the execution of the instructions proceeds to the changed instruction, the content of the instruction buffer is invalidated.

    摘要翻译： 在具有指令缓冲器的数据处理系统中，存储在主存储器中的指令与存储在指令缓冲器中的相同指令之间的不一致在存储操作时发生到存储器，如果提供给主存储器的存储区域的指令 先前已经存储了存储在指令缓冲器中的存储器。 基于从存储器提取的指令的指令获取地址到指令，检测预先指定到指令缓冲器的指令的内容的存储器的改变以及要改变的指令将被执行的事实的改变 缓冲器，要执行的下一条指令的指令地址，存储有要执行的指令的字节位置的信息，改变的指令存储在主存储器中的存储地址以及关于在主存储器中的字节位置的信息 由存储操作改变的指令的主存储。 当指令的执行进行到改变的指令时，指令缓冲器的内容无效。