公开(公告)号：US6054885A

公开(公告)日：2000-04-25

申请号：US123462

申请日：1998-07-28

申请人： Tsukasa Ooishi ,  Tomoya Kawagoe ,  Hideto Hidaka ,  Mikio Asakura

发明人： Tsukasa Ooishi ,  Tomoya Kawagoe ,  Hideto Hidaka ,  Mikio Asakura

IPC分类号： G11C11/403 ,  G06F1/04 ,  G06F1/08 ,  G11C11/401 ,  G11C11/406 ,  G11C11/4076 ,  G11C29/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50

CPC分类号： G11C29/028 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/50 ,  G11C29/50012 ,  G11C11/401

摘要： A tester is connected to a signal output terminal provided in a DRAM chip, and a frequency of a clock signal output from an internal timer is monitored. The frequency of the clock signal is varied by changing the combination of 3 bit signals, so as to obtain signals by which the frequency closest to the set value is obtained. A fuse in the internal timer is disconnected to set the frequency of the clock signal so as to obtain the same state as in the case where that signal is applied.

摘要翻译： 测试器连接到设置在DRAM芯片中的信号输出端子，并且监视从内部定时器输出的时钟信号的频率。 通过改变3位信号的组合来改变时钟信号的频率，以获得最接近设定值的频率的信号。 内部定时器中的保险丝断开以设置时钟信号的频率，以获得与施加该信号的情况相同的状态。

公开(公告)号：US5828258A

公开(公告)日：1998-10-27

申请号：US639326

申请日：1996-04-25

申请人： Tsukasa Ooishi ,  Tomoya Kawagoe ,  Hideto Hidaka ,  Mikio Asakura

发明人： Tsukasa Ooishi ,  Tomoya Kawagoe ,  Hideto Hidaka ,  Mikio Asakura

IPC分类号： G11C11/403 ,  G06F1/04 ,  G06F1/08 ,  G11C11/401 ,  G11C11/406 ,  G11C11/4076 ,  G11C29/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50

CPC分类号： G11C29/028 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/50 ,  G11C29/50012 ,  G11C11/401

摘要： A tester is connected to a signal output terminal provided in a DRAM chip, and a frequency of a clock signal output from an internal timer is monitored. The frequency of the clock signal is varied by changing the combination of 3 bit signals, so as to obtain signals by which the frequency closest to the set value is obtained. A fuse in the internal timer is disconnected to set the frequency of the clock signal so as to obtain the same state as in the case where that signal is applied.

公开(公告)号：US06690241B2

公开(公告)日：2004-02-10

申请号：US09539892

申请日：2000-03-31

申请人： Tsukasa Ooishi ,  Tomoya Kawagoe ,  Hideto Hidaka ,  Mikio Asakura

发明人： Tsukasa Ooishi ,  Tomoya Kawagoe ,  Hideto Hidaka ,  Mikio Asakura

IPC分类号： H03B502

CPC分类号： G11C29/028 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/50 ,  G11C29/50012

摘要： A tester is connected to a signal output terminal provided in a DRAM chip, and a frequency of a clock signal output from an internal timer is monitored. The frequency of the clock signal is varied by changing the combination of 3 bit signals, so as to obtain signals by which the frequency closest to the set value is obtained. A fuse in the internal timer is disconnected to set the frequency of the clock signal so as to obtain the same state as in the case where that signal is applied. The internal timer includes an oscillator formed of a plurality of inverters connected in ring shape and a variable capacitance circuit for each inverter. Each variable capacitance circuit includes a plurality of sets of transfer gates, fuses and capacitors connected between the output node of the corresponding inverter and a prescribed potential line.

摘要翻译： 测试器连接到设置在DRAM芯片中的信号输出端子，并且监视从内部定时器输出的时钟信号的频率。 通过改变3位信号的组合来改变时钟信号的频率，以获得最接近设定值的频率的信号。 内部定时器中的保险丝断开以设置时钟信号的频率，以获得与施加该信号的情况相同的状态。 内部定时器包括由环形连接的多个逆变器和每个逆变器的可变电容电路构成的振荡器。 每个可变电容电路包括连接在相应逆变器的输出节点和规定电位线之间的多组传输门，熔丝和电容器。

公开(公告)号：US06421286B1

公开(公告)日：2002-07-16

申请号：US09978819

申请日：2001-10-18

申请人： Jun Ohtani ,  Tsukasa Ooishi ,  Hideto Hidaka ,  Tomoya Kawagoe

发明人： Jun Ohtani ,  Tsukasa Ooishi ,  Hideto Hidaka ,  Tomoya Kawagoe

IPC分类号： G11C700

CPC分类号： G11C29/72 ,  G11C29/44

摘要： Built-in self-test circuit and built-in redundancy analysis circuit are provided commonly to plural DRAM cores. Built-in redundancy analysis circuit determines a defective address to be replaced with one of plural spare memory cell rows and plural spare memory cell columns according to an address signal and a detection result of a defective memory cell from built-in self-test circuit. Built-in redundancy analysis circuit controls an effective service area of an address storage circuit into which a defective address is stored according to a capacity of a DRAM core to be tested.

摘要翻译： 内置自检电路和内置冗余分析电路通常提供给多个DRAM内核。 内置冗余分析电路根据地址信号和内置的自检电路中的有缺陷的存储单元的检测结果来确定要被多个备用存储单元行和多个备用存储单元列中的一个替换的缺陷地址。 内置冗余分析电路根据要测试的DRAM内核的容量来控制存储有缺陷地址的地址存储电路的有效服务区域。

公开(公告)号：US20050289441A1

公开(公告)日：2005-12-29

申请号：US11148365

申请日：2005-06-09

申请人： Tomoya Kawagoe ,  Tsukasa Ooishi

发明人： Tomoya Kawagoe ,  Tsukasa Ooishi

IPC分类号： G11C29/00

CPC分类号： G06F11/1008

摘要： In an exclusive OR circuit (XOR gate) constituting an ECC circuit, the drivability of P channel MOS transistors is set larger than the drivability of N channel MOS transistors. Accordingly, the speed of the logic level of an output node being set to an H level from an L level identified as a reset state is increased than the case where the drivability is set equal. Thus, the time required to output a syndrome from a plurality of stages of XOR gates can be reduced to allow execution of error correction processing at high speed.

摘要翻译： 在构成ECC电路的异或电路（异或门）中，将P沟道MOS晶体管的驱动能力设定为大于N沟道MOS晶体管的驱动能力。 因此，与将驾驶性能设定为相等的情况相比，将输出节点的逻辑电平从被识别为复位状态的L电平设定为H电平的速度增加。 因此，可以减少从多级XOR门输出综合征所需的时间，以允许高速执行纠错处理。

公开(公告)号：US07552378B2

公开(公告)日：2009-06-23

申请号：US11148365

申请日：2005-06-09

申请人： Tomoya Kawagoe ,  Tsukasa Ooishi

发明人： Tomoya Kawagoe ,  Tsukasa Ooishi

IPC分类号： G11C29/00

CPC分类号： G06F11/1008

摘要： In an exclusive OR circuit (XOR gate) constituting an ECC circuit, the drivability of P channel MOS transistors is set larger than the drivability of N channel MOS transistors. Accordingly, the speed of the logic level of an output node being set to an H level from an L level identified as a reset state is increased than the case where the drivability is set equal. Thus, the time required to output a syndrome from a plurality of stages of XOR gates can be reduced to allow execution of error correction processing at high speed.

摘要翻译： 在构成ECC电路的异或电路（异或门）中，将P沟道MOS晶体管的驱动能力设定为大于N沟道MOS晶体管的驱动能力。 因此，与将驾驶性能设定为相等的情况相比，将输出节点的逻辑电平从被识别为复位状态的L电平设定为H电平的速度增加。 因此，可以减少从多级XOR门输出综合征所需的时间，以允许高速执行纠错处理。

公开(公告)号：US07652912B2

公开(公告)日：2010-01-26

申请号：US11520563

申请日：2006-09-14

申请人： Tomoya Kawagoe ,  Jun Otani ,  Hideto Hidaka

发明人： Tomoya Kawagoe ,  Jun Otani ,  Hideto Hidaka

IPC分类号： G11C11/00

CPC分类号： G11C11/15

摘要： A nonvolatile semiconductor memory device includes a free layer having first and second magnetic layers magnetized oppositely to each other, and also having a first nonmagnetic layer formed between the first and second magnetic layers, a first fixed layer having a fixed magnetization direction, a second nonmagnetic layer formed between the second magnetic layer and the first fixed layer, a first drive circuit passing a write current through a first write current line in a data write operation, and thereby generating a data write magnetic field acting on magnetization of the free layer, and a second drive circuit passing a spin injection current between the first magnetic layer and the first fixed layer in a data write operation, and thereby exerting a force in the same direction as or in the direction opposite to the magnetization direction of the first fixed layer on the magnetization of the free layer.

摘要翻译： 非易失性半导体存储器件包括具有彼此相对磁化的第一和第二磁性层的自由层，并且还具有形成在第一和第二磁性层之间的第一非磁性层，具有固定的磁化方向的第一固定层，第二非磁性层 形成在第二磁性层和第一固定层之间的第一驱动电路，在数据写入操作中使写入电流通过第一写入电流线的第一驱动电路，从而产生作用于自由层的磁化的数据写入磁场;以及 第二驱动电路在数据写入操作中在第一磁性层和第一固定层之间通过自旋注入电流，从而在与第一固定层的磁化方向相反的方向上施加力或者在与第一固定层的磁化方向相反的方向上施加力 自由层的磁化。

公开(公告)号：US20070064472A1

公开(公告)日：2007-03-22

申请号：US11520563

申请日：2006-09-14

申请人： Tomoya Kawagoe ,  Jun Otani ,  Hideto Hidaka

发明人： Tomoya Kawagoe ,  Jun Otani ,  Hideto Hidaka

IPC分类号： G11C11/00

CPC分类号： G11C11/15

摘要： A nonvolatile semiconductor memory device includes a free layer having first and second magnetic layers magnetized oppositely to each other, and also having a first nonmagnetic layer formed between the first and second magnetic layers, a first fixed layer having a fixed magnetization direction, a second nonmagnetic layer formed between the second magnetic layer and the first fixed layer, a first drive circuit passing a write current through a first write current line in a data write operation, and thereby generating a data write magnetic field acting on magnetization of the free layer, and a second drive circuit passing a spin injection current between the first magnetic layer and the first fixed layer in a data write operation, and thereby exerting a force in the same direction as or in the direction opposite to the magnetization direction of the first fixed layer on the magnetization of the free layer.

摘要翻译： 非易失性半导体存储器件包括具有彼此相对磁化的第一和第二磁性层的自由层，并且还具有形成在第一和第二磁性层之间的第一非磁性层，具有固定的磁化方向的第一固定层，第二非磁性层 形成在第二磁性层和第一固定层之间的第一驱动电路，在数据写入操作中使写入电流通过第一写入电流线的第一驱动电路，从而产生作用于自由层的磁化的数据写入磁场;以及 第二驱动电路在数据写入操作中在第一磁性层和第一固定层之间通过自旋注入电流，从而在与第一固定层的磁化方向相反的方向上施加力或者在与第一固定层的磁化方向相反的方向上施加力 自由层的磁化。

公开(公告)号：US06243307B1

公开(公告)日：2001-06-05

申请号：US09459710

申请日：1999-12-13

申请人： Tomoya Kawagoe

发明人： Tomoya Kawagoe

IPC分类号： G11C700

CPC分类号： G11C29/72

摘要： After writing data into a memory cell array according to an internal address signal, data read out from each memory cell is compared with expected value data in a read out operation. When there are two spare rows and two spare columns provided, a replacement determination unit is provided for each of the sixth types of sequences sequentially replacing a memory cell row and a memory cell column. A defective address is written into four sets of storage cell trains provided corresponding to each replacement determination unit only when a defective memory cell is detected having an address differing from at least one of a row address and column address of a defective memory cell that is already stored.

摘要翻译： 根据内部地址信号将数据写入存储单元阵列后，在读出操作中将从每个存储单元读出的数据与期望值数据进行比较。 当提供两个备用行和两个备用列时，为依次替换存储单元行和存储单元列的第六类型序列中的每一个提供替换确定单元。 仅当检测到具有与已经存在的有缺陷的存储器单元的行地址和列地址中的至少一个不同的地址的缺陷存储单元时，将有缺陷的地址写入与每个替换确定单元相对应的4组存储单元列中 存储。

公开(公告)号：US5475268A

公开(公告)日：1995-12-12

申请号：US357282

申请日：1994-12-13

申请人： Tomoya Kawagoe ,  Akihisa Oishi ,  Mitsutaka Niiro ,  Katsumi Dosaka

发明人： Tomoya Kawagoe ,  Akihisa Oishi ,  Mitsutaka Niiro ,  Katsumi Dosaka

IPC分类号： H01L21/68 ,  H01L21/027 ,  H01L21/822 ,  H01L23/544 ,  H01L27/04 ,  H01L23/48 ,  H01L23/522

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002

摘要： A semiconductor device having an alignment mark which is improved to enable accurate recognition of the alignment mark is provided. A first interconnection layer is provided on a semiconductor substrate. A second interconnection layer is provided on an interlayer insulating film so that first and second interconnection layers cross each other with interlayer insulating film therebetween. A surface of second interconnection layer includes, in a region where first and second interconnection layers cross each other, a flat portion which reflects laser beam vertically and upwardly and a portion including concaves and convexes which reflects laser beam irregularly, which together form an alignment mark.

摘要翻译： 提供了具有对准标记的半导体器件，其被改进以能够准确地识别对准标记。 第一互连层设置在半导体衬底上。 第二互连层设置在层间绝缘膜上，使得第一互连层和第二互连层之间具有层间绝缘膜彼此交叉。 第二互连层的表面在第一和第二互连层彼此交叉的区域中包括反射激光束垂直和向上的平坦部分和包括不规则地反射激光束的凹凸部分，这些部分一起形成对准标记 。