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公开(公告)号：US06507884B1
公开(公告)日：2003-01-14
申请号：US09218768
申请日：1998-12-22
IPC分类号： G06F1200
CPC分类号： G06F12/06 , G06F12/04 , G11C16/102
摘要： A selection circuit causes either a memory 6H or 6L to enter an enabled state according to address data A16 of address data A0-A16 when a mode signal M is 1. The selection circuit comprises OR gates (10, 12) which output different outputs. When the address data A16 is 0, a nonvolatile memory 6L enters an enabled state. Then, the memory 6L is addressed according to the address data A0-A15 so that, for example, 8-bit lower data is written therein. On the other hand, when the address data A16 is 1, a nonvolatile memory 6H becomes in an enabled state. Then, the memory 6H is addressed according to the address data A0-A15 so that, for example, 8-bit upper data is written therein. Also, when an external terminal (17) is grounded, and a mode signal become 0, the OR gates (10, 12) outputs signals 0, so that the memories 6H, 6L simultaneously become in an enabled state. When data is read from corresponding addresses of each memory, data of, for example, 16-bits is obtained.
摘要翻译： 当模式信号M为1时，选择电路使得存储器6H或6L根据地址数据A0-A16的地址数据A16进入使能状态。选择电路包括输出不同输出的或门（10,12）。 当地址数据A16为0时，非易失性存储器6L进入使能状态。 然后，根据地址数据A0-A15对存储器6L进行寻址，以便例如在其中写入8位较低的数据。 另一方面，当地址数据A16为1时，非易失性存储器6H变为使能状态。 然后，根据地址数据A0-A15对存储器6H进行寻址，使得例如在其中写入8位上位数据。 此外，当外部端子（17）接地并且模式信号变为0时，或门（10,12）输出信号0，使得存储器6H，6L同时变为使能状态。 当从每个存储器的相应地址读取数据时，获得例如16位的数据。
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2.发明授权公开(公告)号：US06298412B1
公开(公告)日：2001-10-02
申请号：US09218944
申请日：1998-12-22
IPC分类号： G06F1202
CPC分类号： G06F15/7814 , G11C16/102
摘要： When writing of data into nonvolatile memories 8H and 8L is started, data D7 and D15 corresponding to the 128th word of a data input section 8B are inverted and outputted. When accurate writing is subsequently performed, the data D7 and D15 are outputted as they are. By monitoring a change of the data D7 and D15 from the nonvolatile memories 8H and 8L, it is possible to detect whether writing is still continuing or has already completed. Thus, by using nonvolatile memories of 8 bit data width or the like, a 16-bit microcomputer can be easily realized.
摘要翻译： 当将数据写入非易失性存储器8H和8L时，与数据输入部分8B的第128个字对应的数据D7和D15被反相输出。 当随后执行精确写入时，数据D7和D15原样输出。 通过监视来自非易失性存储器8H和8L的数据D7和D15的变化，可以检测写入是否仍在继续或已经完成。 因此，通过使用8位数据宽度等的非易失性存储器，可以容易地实现16位微型计算机。
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3.发明授权Circuit for prevention of unintentional writing to a memory, and semiconductor device equipped with said circuit 有权用于防止对存储器的无意写入的电路以及配备有所述电路的半导体器件公开(公告)号：US07213120B2
公开(公告)日：2007-05-01
申请号：US10809866
申请日：2004-03-26
申请人： Kazuo Hotaka
发明人： Kazuo Hotaka
IPC分类号： G06F12/14
CPC分类号： G11C16/225
摘要： A circuit for prevention of unintentional writing to a memory prevents unintentional writing to a nonvolatile memory, after a recovery from a transitory power failure. The circuit includes a low-voltage detection circuit for detecting a power supply voltage drop depending on the state of a control signal for the detection circuit. A writing operation to the memory is prohibited depending on the control signal as well as upon an output signal of the low-voltage detection circuit.
摘要翻译： 用于防止对存储器的无意写入的电路在从暂时断电恢复之后防止对非易失性存储器的无意写入。 该电路包括用于根据检测电路的控制信号的状态来检测电源电压降的低电压检测电路。 根据控制信号以及低电压检测电路的输出信号，禁止对存储器的写入操作。
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公开(公告)号：US06349057B2
公开(公告)日：2002-02-19
申请号：US09892984
申请日：2001-06-27
申请人： Kazuo Hotaka
发明人： Kazuo Hotaka
IPC分类号： G11C1604
摘要： A read protection memory area is formed within the same memory mat as a main memory area, so that the need to dedicatedly provide a dedicated EEPROM cell for storing read protection data and an analog control circuit for writing the read protection data into this EEPROM cell is eliminated and a chip size can be reduced.
摘要翻译： 读取保护存储器区域形成在与主存储区域相同的存储器堆中，因此需要专门提供用于存储读保护数据的专用EEPROM单元和用于将读保护数据写入该EEPROM单元的模拟控制电路， 并且可以减小芯片尺寸。
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公开(公告)号：US07683652B2
公开(公告)日：2010-03-23
申请号：US11812509
申请日：2007-06-19
申请人： Naoto Morishita , Kazuo Hotaka
发明人： Naoto Morishita , Kazuo Hotaka
摘要： A low-voltage detection circuit detects a low voltage using a voltage follower type operational amplifier and an A/D converter instead of a conventional low-voltage detection circuit. That is, a reference voltage is applied from a reference voltage generating circuit to the A/D converter through the voltage follower type operational amplifier. The voltage follower type operational amplifier is used to reduce output impedance. The power supply voltage can be detected by a converted value (a digital value) from the A/D converter since the reference voltage is independent of the power supply voltage and the converted value varies depending on the power supply voltage. The converted value (the digital value) from the A/D converter is set in a register and statuses of a microcomputer are set as in the conventional art, using the converted value as a flag.
摘要翻译： 低电压检测电路使用电压跟随器型运算放大器和A / D转换器代替传统的低电压检测电路来检测低电压。 也就是说，通过电压跟随器型运算放大器将参考电压从基准电压产生电路施加到A / D转换器。 电压跟随器型运算放大器用于降低输出阻抗。 电源电压可以通过来自A / D转换器的转换值（数字值）来检测，因为参考电压与电源电压无关，并且转换值根据电源电压而变化。 将来自A / D转换器的转换值（数字值）设置在寄存器中，并且将传统技术中的转换值用作标志来设置微型计算机的状态。
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公开(公告)号：US20080012604A1
公开(公告)日：2008-01-17
申请号：US11812509
申请日：2007-06-19
申请人： Naoto Morishita , Kazuo Hotaka
发明人： Naoto Morishita , Kazuo Hotaka
IPC分类号： H03K5/22
摘要： A low-voltage detection circuit that is small in size and accurate in detecting a reduction in a power supply voltage is offered. The low-voltage detection circuit of an embodiment of this invention detects a low voltage using a voltage follower type operational amplifier and an A/D converter instead of a conventional low-voltage detection circuit. That is, a reference voltage Vref is applied from a reference voltage generating circuit to the A/D converter through the voltage follower type operational amplifier. The voltage follower type operational amplifier is used to reduce output impedance. The power supply voltage Vdd can be detected by a converted value (a digital value) from the A/D converter since the reference voltage Vref is independent of the power supply voltage Vdd and the converted value varies depending on the power supply voltage Vdd. The converted value (the digital value) from the A/D converter is set in a register and statuses of a microcomputer are set as in the conventional art, using the converted value as a flag.
摘要翻译： 提供了一种尺寸小且准确地检测电源电压降低的低电压检测电路。 本发明实施例的低电压检测电路使用电压跟随器型运算放大器和A / D转换器代替传统的低电压检测电路来检测低电压。 也就是说，通过电压跟随器型运算放大器将参考电压Vref从基准电压产生电路施加到A / D转换器。 电压跟随器型运算放大器用于降低输出阻抗。 电源电压Vdd可以通过来自A / D转换器的转换值（数字值）来检测，因为参考电压Vref与电源电压Vdd无关，并且转换值根据电源电压Vdd而变化。 将来自A / D转换器的转换值（数字值）设置在寄存器中，并且将传统技术中的转换值用作标志来设置微型计算机的状态。
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7.发明申请公开(公告)号：US20050117396A1
公开(公告)日：2005-06-02
申请号：US10980960
申请日：2004-11-03
申请人： Kazuo Hotaka
发明人： Kazuo Hotaka
IPC分类号： G11C17/00 , G06F11/00 , G06F15/78 , G11C16/02 , G11C16/06 , G11C16/28 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/28
摘要： Disclosed are a semiconductor storage apparatus and a microcomputer incorporating the same. The semiconductor storage apparatus has a nonvolatile memory and a first sense amplifier comparing the level of a read-out signal read out from the nonvolatile memory with a first reference level. The semiconductor storage apparatus comprises a detector operable to output, when detecting that a difference between the level of the read-out signal and the first reference level is smaller than a predetermined level difference, a detection signal indicative of the difference being smaller than the predetermined level difference.
摘要翻译： 公开了一种半导体存储装置和包含该半导体存储装置的微型计算机。 半导体存储装置具有非易失性存储器和第一读出放大器，其将从非易失性存储器读出的读出信号的电平与第一参考电平进行比较。 半导体存储装置包括检测器，其可操作以在检测到读出信号的电平与第一参考电平之间的差小于预定电平差时输出表示差异小于预定电平差的检测信号 水平差异。
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公开(公告)号：US07453295B2
公开(公告)日：2008-11-18
申请号：US11812510
申请日：2007-06-19
申请人： Kazuo Hotaka
发明人： Kazuo Hotaka
IPC分类号： H03L7/00
CPC分类号： H03K3/356008
摘要： A low-voltage detection reset circuit that suppresses a current consumption in a stand-by mode and is reduced in a size is offered. The low-voltage detection reset circuit is provided with a power-on reset circuit that operates only at power-on and outputs a reset pulse and is configured to set a detection level of a detection level setting circuit at a default value using the reset pulse and to activate a programmable low-voltage detection circuit. After the programmable low-voltage detection circuit is activated, a detection level of the programmable low-voltage detection circuit can be modified from the default value by a register.
摘要翻译： 提供了抑制待机模式中的电流消耗并减小尺寸的低电压检测复位电路。 低电压检测复位电路具有上电复位电路，其仅在上电时工作并输出复位脉冲，并且被配置为使用复位脉冲将检测电平设置电路的检测电平设置为默认值 并激活可编程低电压检测电路。 在可编程低电压检测电路被激活之后，可以通过寄存器从默认值修改可编程低电压检测电路的检测电平。
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公开(公告)号：US20080012613A1
公开(公告)日：2008-01-17
申请号：US11812510
申请日：2007-06-19
申请人： Kazuo Hotaka
发明人： Kazuo Hotaka
CPC分类号： H03K3/356008
摘要： A low-voltage detection reset circuit that suppresses a current consumption in a stand-by mode and is reduced in a size is offered. The low-voltage detection reset circuit is provided with a power-on reset circuit that operates only at power-on and outputs a reset pulse and is configured to set a detection level of a detection level setting circuit at a default value using the reset pulse and to activate a programmable low-voltage detection circuit. After the programmable low-voltage detection circuit is activated, a detection level of the programmable low-voltage detection circuit can be modified from the default value by a register.
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10.发明授权公开(公告)号：US07079418B2
公开(公告)日：2006-07-18
申请号：US10980960
申请日：2004-11-03
申请人： Kazuo Hotaka
发明人： Kazuo Hotaka
CPC分类号： G11C16/28
摘要： Disclosed are a semiconductor storage apparatus and a microcomputer incorporating the same. The semiconductor storage apparatus has a nonvolatile memory and a first sense amplifier comparing the level of a read-out signal read out from the nonvolatile memory with a first reference level. The semiconductor storage apparatus comprises a detector operable to output, when detecting that a difference between the level of the read-out signal and the first reference level is smaller than a predetermined level difference, a detection signal indicative of the difference being smaller than the predetermined level difference.
摘要翻译： 公开了一种半导体存储装置和包含该半导体存储装置的微型计算机。 半导体存储装置具有非易失性存储器和第一读出放大器，其将从非易失性存储器读出的读出信号的电平与第一参考电平进行比较。 半导体存储装置包括检测器，其可操作以在检测到读出信号的电平与第一参考电平之间的差小于预定电平差时输出表示差异小于预定电平差的检测信号 水平差异。
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