公开(公告)号：US07061511B2

公开(公告)日：2006-06-13

申请号：US10756510

申请日：2004-01-14

申请人： Tsutomu Furuhashi ,  Tatsuhiro Inuzuka ,  Hiroshi Kurihara ,  Kikuo Ono

发明人： Tsutomu Furuhashi ,  Tatsuhiro Inuzuka ,  Hiroshi Kurihara ,  Kikuo Ono

IPC分类号： G09G5/10

CPC分类号： G09G3/3611 ,  G09G5/39 ,  G09G2320/02 ,  G09G2320/0252 ,  G09G2320/0261 ,  G09G2340/16

摘要： A liquid crystal display device in which the time necessary for luminance to change from application of a different gray-scale voltage exceeds one frame period in relation to the response as a luminance change time of the liquid crystal. The liquid crystal display device includes a signal control circuit for preventing the content of a preceding frame from being displayed as an after-image and preventing also deterioration of image quality. The signal control circuit includes a frame memory for delaying by one frame the first display data inputted from the external device, an arithmetic operation circuit for comparing the second display data stored in the frame memory and delayed by one frame with the first display data, and an addition/subtraction circuit for adding and subtracting correction data outputted by the arithmetic operation circuit to and from the first display data.

摘要翻译： 一种液晶显示装置，其中从应用不同灰度电压变化的亮度所需的时间相对于作为液晶的亮度变化时间的响应而超过一帧周期。 液晶显示装置包括用于防止前一帧的内容被显示为后置图像并且防止图像质量劣化的信号控制电路。 该信号控制电路包括用于将从外部设备输入的第一显示数据延迟一帧的帧存储器，用于将存储在帧存储器中并延迟了一帧的第二显示数据与第一显示数据进行比较的算术运算电路，以及 加法/减法电路，用于将由算术运算电路输出的校正数据与第一显示数据相加和减去。

公开(公告)号：US20050062701A1

公开(公告)日：2005-03-24

申请号：US10756510

申请日：2004-01-14

申请人： Tsutomu Furuhashi ,  Tatsuhiro Inuzuka ,  Hiroshi Kurihara ,  Kikuo Ono

发明人： Tsutomu Furuhashi ,  Tatsuhiro Inuzuka ,  Hiroshi Kurihara ,  Kikuo Ono

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G09G5/39

CPC分类号： G09G3/3611 ,  G09G5/39 ,  G09G2320/02 ,  G09G2320/0252 ,  G09G2320/0261 ,  G09G2340/16

摘要： A liquid crystal display device in which the time necessary for luminance to change from application of a different gray-scale voltage exceeds one frame period in relation to the response as a luminance change time of the liquid crystal. The liquid crystal display device includes a signal control circuit for preventing the content of a preceding frame from being displayed as an after-image and preventing also deterioration of image quality. The signal control circuit includes a frame memory for delaying by one frame the first display data inputted from the external device, an arithmetic operation circuit for comparing the second display data stored in the frame memory and delayed by one frame with the first display data, and an addition/subtraction circuit for adding and subtracting correction data outputted by the arithmetic operation circuit to and from the first display data.

摘要翻译： 一种液晶显示装置，其中从应用不同灰度电压变化的亮度所需的时间相对于作为液晶的亮度变化时间的响应而超过一帧周期。 液晶显示装置包括用于防止前一帧的内容被显示为后置图像并且防止图像质量劣化的信号控制电路。 该信号控制电路包括用于将从外部设备输入的第一显示数据延迟一帧的帧存储器，用于将存储在帧存储器中并延迟了一帧的第二显示数据与第一显示数据进行比较的算术运算电路，以及 加法/减法电路，用于将由算术运算电路输出的校正数据与第一显示数据相加和减去。

公开(公告)号：US06556180B1

公开(公告)日：2003-04-29

申请号：US09655826

申请日：2000-09-06

申请人： Tsutomu Furuhashi ,  Tatsuhiro Inuzuka ,  Hiroshi Kurihara ,  Kikuo Ono

发明人： Tsutomu Furuhashi ,  Tatsuhiro Inuzuka ,  Hiroshi Kurihara ,  Kikuo Ono

IPC分类号： G09G336

CPC分类号： G09G3/3611 ,  G09G5/39 ,  G09G2320/02 ,  G09G2320/0252 ,  G09G2320/0261 ,  G09G2340/16

摘要： A liquid crystal display device in which the time necessary for luminance to change from application of a different gray-scale voltage exceeds one frame period in relation to the response as a luminance change time of the liquid crystal. The liquid crystal display device includes a signal control circuit for preventing the content of a preceding frame from being displayed as an after-image and preventing also deterioration of image quality. The signal control circuit includes a frame memory for delaying by one frame the first display data inputted from the external device, an arithmetic operation circuit for comparing the second display data stored in the frame memory and delayed by one frame with the first display data, and an addition/subtraction circuit for adding and subtracting correction data outputted by the arithmetic operation circuit to and from the first display data.

摘要翻译： 一种液晶显示装置，其中从应用不同灰度电压变化的亮度所需的时间相对于作为液晶的亮度变化时间的响应而超过一帧周期。 液晶显示装置包括用于防止前一帧的内容被显示为后置图像并且防止图像质量劣化的信号控制电路。 该信号控制电路包括用于将从外部设备输入的第一显示数据延迟一帧的帧存储器，用于将存储在帧存储器中并延迟了一帧的第二显示数据与第一显示数据进行比较的算术运算电路，以及 加法/减法电路，用于将由算术运算电路输出的校正数据与第一显示数据相加和减去。

公开(公告)号：US06714181B2

公开(公告)日：2004-03-30

申请号：US10361647

申请日：2003-02-11

申请人： Tsutomu Furuhashi ,  Tatsuhiro Inuzuka ,  Hiroshi Kurihara ,  Kikuo Ono

发明人： Tsutomu Furuhashi ,  Tatsuhiro Inuzuka ,  Hiroshi Kurihara ,  Kikuo Ono

IPC分类号： G09G336

CPC分类号： G09G3/3611 ,  G09G5/39 ,  G09G2320/02 ,  G09G2320/0252 ,  G09G2320/0261 ,  G09G2340/16

摘要： A liquid crystal display device in which the time necessary for luminance to change from application of a different gray-scale voltage exceeds one frame period in relation to the response as a luminance change time of the liquid crystal. The liquid crystal display device includes a signal control circuit for preventing the content of a preceding frame from being displayed as an after-image and preventing also deterioration of image quality. The signal control circuit includes a frame memory for delaying by one frame the first display data inputted from the external device, an arithmetic operation circuit for comparing the second display data stored in the frame memory and delayed by one frame with the first display data, and an addition/subtraction circuit for adding and subtracting correction data outputted by the arithmetic operation circuit to and from the first display data.

摘要翻译： 一种液晶显示装置，其中从应用不同灰度电压变化的亮度所需的时间相对于作为液晶的亮度变化时间的响应而超过一帧周期。 液晶显示装置包括用于防止前一帧的内容被显示为后置图像并且防止图像质量劣化的信号控制电路。 该信号控制电路包括用于将从外部设备输入的第一显示数据延迟一帧的帧存储器，用于将存储在帧存储器中并延迟了一帧的第二显示数据与第一显示数据进行比较的算术运算电路，以及 加法/减法电路，用于将由算术运算电路输出的校正数据与第一显示数据相加和减去。

公开(公告)号：US07158107B2

公开(公告)日：2007-01-02

申请号：US09805190

申请日：2001-03-14

申请人： Kazuyoshi Kawabe ,  Tsutomu Furuhashi ,  Tatsuhiro Inuzuka ,  Hiroshi Kurihara ,  Kikuo Ono

发明人： Kazuyoshi Kawabe ,  Tsutomu Furuhashi ,  Tatsuhiro Inuzuka ,  Hiroshi Kurihara ,  Kikuo Ono

IPC分类号： G09G3/36

CPC分类号： G09G3/3611 ,  G09G3/3648 ,  G09G2320/0223 ,  G09G2320/0252 ,  G09G2320/0261 ,  G09G2320/103 ,  G09G2340/16

摘要： The present invention includes: a liquid crystal panel 105 on which is formed a matrix of a plurality of image elements; a correction circuit 107 that receives a video data gradation signal input, generates a correction signal for correcting luminance using a relationship defined by the gradation level from an input gradation for an (N−1)-th frame and the gradation level from an input gradation for an N-th frame, and corrects the input gradation signal for the N-th frame using the correction signal; a data driver 109 generating a write potential based on the corrected input gradation signal for the N-th frame and applies the potential to an image element; and a scan driver selecting an image element to which the write potential is applied.

摘要翻译： 本发明包括：液晶面板105，其上形成有多个图像元素的矩阵; 接收视频数据灰度信号输入的校正电路107根据第（N-1）帧的输入灰度和来自输入灰度等级的灰度等级，使用由灰度级定义的关系来校正亮度的校正信号 并且使用校正信号来校正第N帧的输入灰度信号; 数据驱动器109，基于用于第N帧的经校正的输入灰度信号产生写入电位，并将该电位施加到图像元素; 以及扫描驱动器，选择施加写入电位的图像元素。

公开(公告)号：US20060187174A1

公开(公告)日：2006-08-24

申请号：US11407976

申请日：2006-04-21

申请人： Tsutomu Furuhashi ,  Takeshi Maeda ,  Atsuhiro Higa ,  Hisayuki Ohhara ,  Hiroshi Kurihara ,  Naruhiko Kasai

发明人： Tsutomu Furuhashi ,  Takeshi Maeda ,  Atsuhiro Higa ,  Hisayuki Ohhara ,  Hiroshi Kurihara ,  Naruhiko Kasai

IPC分类号： G09G3/36

CPC分类号： G09G5/005 ,  G09G3/3611 ,  G09G3/3685 ,  G09G3/3688 ,  G09G5/003 ,  G09G5/006 ,  G09G5/391 ,  G09G5/393 ,  G09G5/395 ,  G09G2310/0205 ,  G09G2310/027 ,  G09G2340/0407 ,  G09G2340/0414 ,  G09G2340/0421 ,  G09G2340/0435 ,  G09G2340/0471 ,  G09G2340/0478 ,  G09G2340/0485 ,  G09G2360/18

摘要： There is provided a liquid crystal display control device which can display pictures in a magnification mode by using only a memory having low-speed access and a low storage capacity. When a video signal has intermediate resolution or less, the enlargement processing is performed by a frame memory, a line memory and an enlargement processing control circuit. If the input operation and the output operation to and from the frame memory are synchronized with each other, it is sufficient for the frame memory to have a storage capacity of two lines. When the video signal has the same high resolution as a liquid crystal display panel, the video signal is output through a gate circuit to a display timing generating circuit, and it is displayed in a through mode. In this case, no processing is performed by the frame memory or the like.

公开(公告)号：US06628260B2

公开(公告)日：2003-09-30

申请号：US09928413

申请日：2001-08-14

申请人： Tsutomu Furuhashi ,  Takeshi Maeda ,  Atsuhiro Higa ,  Hisayuki Ohhara ,  Hiroshi Kurihara ,  Naruhiko Kasai

发明人： Tsutomu Furuhashi ,  Takeshi Maeda ,  Atsuhiro Higa ,  Hisayuki Ohhara ,  Hiroshi Kurihara ,  Naruhiko Kasai

IPC分类号： G09G336

CPC分类号： G09G5/005 ,  G09G3/3611 ,  G09G3/3685 ,  G09G3/3688 ,  G09G5/003 ,  G09G5/006 ,  G09G5/391 ,  G09G5/393 ,  G09G5/395 ,  G09G2310/0205 ,  G09G2310/027 ,  G09G2340/0407 ,  G09G2340/0414 ,  G09G2340/0421 ,  G09G2340/0435 ,  G09G2340/0471 ,  G09G2340/0478 ,  G09G2340/0485 ,  G09G2360/18

摘要： There is provided a liquid crystal display control device which can display pictures in a magnification mode by using only a memory having low-speed access and a low storage capacity. When a video signal has intermediate resolution or less, the enlargement processing is performed by a frame memory, a line memory and an enlargement processing control circuit. If the input operation and the output operation to and from the frame memory are synchronized with each other, it is sufficient for the frame memory to have a storage capacity of two lines. When the video signal has the same high resolution as a liquid crystal display panel, the video signal is output through a gate circuit to a display timing generating circuit, and it is displayed in a through mode. In this case, no processing is performed by the frame memory or the like.

公开(公告)号：US06515676B1

公开(公告)日：2003-02-04

申请号：US09603967

申请日：2000-06-26

申请人： Naruhiko Kasai ,  Tsutomu Furuhashi ,  Hiroshi Kurihara ,  Nobutaka Kato ,  Masashi Mori ,  Yukio Hiruta

发明人： Naruhiko Kasai ,  Tsutomu Furuhashi ,  Hiroshi Kurihara ,  Nobutaka Kato ,  Masashi Mori ,  Yukio Hiruta

IPC分类号： G09G336

CPC分类号： G09G5/222 ,  G09G3/2007 ,  G09G3/3611

摘要： In a liquid crystal display apparatus having a liquid crystal display panel, an input analog display data is converted to a digital display data, a data portion is selected from the digital display data, and display status information is displayed on the display panel in the form of an overlay display data over the digital display data, so that display adjustment on the display panel is possible. The display adjustment may be automatically performed by use of a minimum value data and a maximum value data, found among the digital display data, for an automatic offset level adjustment and for an automatic gain level adjustment, respectively.

摘要翻译： 在具有液晶显示面板的液晶显示装置中，将输入的模拟显示数据转换为数字显示数据，从数字显示数据中选择数据部分，并以显示面板的形式显示显示状态信息 通过数字显示数据覆盖显示数据，使得显示面板上的显示调整成为可能。 可以通过使用在数字显示数据中找到的最小值数据和最大值数据来分别进行自动偏移电平调整和自动增益电平调整来自动执行显示调整。

公开(公告)号：US06448976B1

公开(公告)日：2002-09-10

申请号：US09044522

申请日：1998-03-19

申请人： Hiroyuki Nitta ,  Atsuhiro Higa ,  Masashi Nakamura ,  Tsutomu Furuhashi ,  Satoru Tsunekawa ,  Hiroshi Kurihara

发明人： Hiroyuki Nitta ,  Atsuhiro Higa ,  Masashi Nakamura ,  Tsutomu Furuhashi ,  Satoru Tsunekawa ,  Hiroshi Kurihara

IPC分类号： G09G502

CPC分类号： G09G3/3685 ,  G09G2340/0407 ,  G09G2340/0485

摘要： A liquid crystal drive circuit, which makes it possible to display low resolution display data on a high resolution liquid crystal panel while expanding and/or centering the display data, is provided. A multiscan control signal is inputted to a latch address control circuit and a data control circuit to control latch signals and the display data so as to latch single pixel data into a plurality of latches at the same time. The display data are latched with the expanding and/or centering operation, and outputted in synchronization with a line clock after being converted to gray scale voltages. Accordingly, it is possible to realize the lateral expansion and/or the centering operation. Further, it is also possible to realize a longitudinal expansion by adding a latch circuit between a latch circuit and a liquid crystal applied voltage generation circuit, and by outputting the data in synchronization with an expanded line clock.

摘要翻译： 提供一种液晶驱动电路，其能够在扩大和/或使显示数据居中的同时在高分辨率液晶面板上显示低分辨率显示数据。 多存储控制信号被输入到锁存地址控制电路和数据控制电路，以控制锁存信号和显示数据，以将单个像素数据同时锁存在多个锁存器中。 显示数据以扩展和/或定心操作被锁存，并且在被转换成灰度级电压之后与行时钟同步地输出。 因此，可以实现横向膨胀和/或定心操作。 此外，还可以通过在锁存电路和液晶施加电压产生电路之间添加锁存电路，并且通过与扩展的线时钟同步地输出数据来实现纵向扩展。

公开(公告)号：US06340970B1

公开(公告)日：2002-01-22

申请号：US09264872

申请日：1999-03-09

申请人： Tsutomu Furuhashi ,  Satoshi Konuma ,  Tatsumi Mori ,  Hiroshi Kurihara ,  Shigeyuki Nishitani ,  Masashi Mori ,  Takeshi Maeda

发明人： Tsutomu Furuhashi ,  Satoshi Konuma ,  Tatsumi Mori ,  Hiroshi Kurihara ,  Shigeyuki Nishitani ,  Masashi Mori ,  Takeshi Maeda

IPC分类号： G09G500

CPC分类号： G09G5/008 ,  G09G5/399 ,  G09G2310/0224

摘要： A liquid crystal display control device is provided with a clock generating circuit for generating, on the basis of a first synchronous signal, a 1/n-frequency dot clock whose period is equal to n-times the dot period of a first video signal (n≧2) and whose phase varies on dot-period basis for every frame period of the first video signal, an input circuit for picking up the first video signal in accordance with the 1/n-frequency dot clock and outputting digital display data, a frame memory in which the digital display data are stored, and a control circuit for generating a second synchronous signal for a liquid crystal display and reading out the display data stored in the frame memory to generate a second video signal, whereby a series of operations from a pickup operation of the video signal to a display operation of the liquid crystal panel can be performed at a lower speed while suppressing deterioration in quality of display images.

摘要翻译： 液晶显示控制装置设置有时钟发生电路，用于根据第一同步信号产生周期等于第一视频信号的点周期的n倍的1 / n频点时钟 n> = 2），并且其相位在第一视频信号的每个帧周期的基于点周期的基础上变化，用于根据1 / n频点时钟拾取第一视频信号并输出​​数字显示数据的输入电路 存储数字显示数据的帧存储器和用于产生用于液晶显示器的第二同步信号并读出存储在帧存储器中的显示数据以产生第二视频信号的控制电路，由此一系列 可以以更低的速度执行从视频信号的拾取操作到液晶面板的显示操作的操作，同时抑制显示图像的质量的劣化。