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40 条记录 (耗时 0.036 秒)

    FMX stereophonic broadcast receiver
    1.
    发明授权
    FMX stereophonic broadcast receiver 失效
    FMX立体声广播接收机

    公开(公告)号：US4864637A

    公开(公告)日：1989-09-05

    申请号：US195106

    申请日：1988-05-16

    申请人： Tsutomu Ishikawa ,  Noboru Usui ,  Kanji Tanaka ,  Ryuichi Ogawa ,  Kazuhisa Ishiguro ,  Masashi Arai

    发明人： Tsutomu Ishikawa ,  Noboru Usui ,  Kanji Tanaka ,  Ryuichi Ogawa ,  Kazuhisa Ishiguro ,  Masashi Arai

    IPC分类号： H04B1/16

    CPC分类号： H04B1/1692

    摘要： An improved FMX sterophonic broadcast receiver provided with countermeasures against transient noises, which includes a level detection circuit for detecting level of a detected stereo difference signal, and a level control circuit for controlling level of an expanded stereo difference signal according to an output signal of the level detection circuit. By the above arrangement of the present invention, since it is so arranged to cause the level control circuit to function when the degree of modulation becomes large so as to control the level of the stereo difference signal to be low, a level difference is produced between the stereo sum signal and the stereo difference signal for deterioration of the stereo separation degree upon matrixing at a matrix circuit for reduction of noises accordingly.

    FMX stereophonic receiver
    2.
    发明授权
    FMX stereophonic receiver 失效
    FMX立体声接收机

    公开(公告)号：US4852167A

    公开(公告)日：1989-07-25

    申请号：US143805

    申请日：1988-01-14

    申请人： Noboru Usui ,  Kanji Tanaka ,  Ryuichi Ogawa ,  Tsutomu Ishikawa ,  Kazuhisa Ishiguro ,  Masashi Arai

    发明人： Noboru Usui ,  Kanji Tanaka ,  Ryuichi Ogawa ,  Tsutomu Ishikawa ,  Kazuhisa Ishiguro ,  Masashi Arai

    IPC分类号： H03G7/00 ,  H04B1/16

    CPC分类号： H04B1/1692 ,  H03G7/008

    摘要： An FMX stereophonic receiver receives an FMX stereophonic broadcast signal which includes a stereo sum signal, an uncompressed stereo difference signal, and a compressed stereo difference signal which is formed by modulating the uncompressed stereo difference signal by a quadrature modulation and being compressed. The FMX stereophonic receiver includes an FM detector for producing an FM detection signal including a stereo pilot signal, a PLL circuit for producing a signal which is in a synchronized relationship with the stereo pilot signal included in the FM detection signal, a synchronous detection circuit for receiving the FM detection signal and for producing the uncompressed stereo difference signal in accordance with the signal produced from the PLL circuit, a quadrature detection circuit for receiving the FM detection signal and for producing the compressed stereo difference signal in accordance with the signal produced from the PLL circuit, and a phase shifting means for shifting the phase of at least one of the FM detection signal applied to the PLL circuit and the FM detection signal applied to the detection circuits so as to correct the phase difference between the synchronous detection signal and the signal to be detected.

    FM/FMX stereophonic receiver
    3.
    发明授权
    FM/FMX stereophonic receiver 失效
    FM / FMX立体声接收机

    公开(公告)号：US4809328A

    公开(公告)日：1989-02-28

    申请号：US157048

    申请日：1988-02-16

    申请人： Noboru Usui ,  Kanji Tanaka ,  Ryuichi Ogawa ,  Tsutomu Ishikawa ,  Kazuhisa Ishiguro ,  Masashi Arai

    发明人： Noboru Usui ,  Kanji Tanaka ,  Ryuichi Ogawa ,  Tsutomu Ishikawa ,  Kazuhisa Ishiguro ,  Masashi Arai

    IPC分类号： H04B1/16 ,  H04H5/00

    CPC分类号： H04B1/1692

    摘要： An FM/FMX stereophonic receiver is capable of receiving an FM or an FMX stereophonic broadcast signal. The FM stereophonic broadcast signal includes a stereo sum signal and stereo difference signal, whereas the FMX stereophonic broadcast signal further includes a compressed stereo difference signal and an FMX ID signal indicating the FMX stereophonic broadcast signal. The FM/FMX stereophonic receiver has a stereo demodulator for receiving said broadcast signal and for producing left and right stereo signals, a detector for detecting the field strength of the receiving signal, and a noise reducer, which may be a circuit for changing the mode from stereophonic mode to monaural mode or a high cut circuit for attenuating the signals of high frequency region, for reducing noise signals contained in the left and right stereo signals. The FM/FMX stereophonic receiver further has a detector for detecting the FMX ID signal and a disabling circuit for disabling the noise reducer when the FMX ID signal is detected by the detector. Instead of the disabling circuit, a timing control circuit may be provided for changing the timing at which the noise reducer starts to activate in response to the detection of the FMX ID signal.

    Variable reactance circuit producing negative to positive varying reactance
    4.
    发明授权
    Variable reactance circuit producing negative to positive varying reactance 失效
    可变电抗电路产生负变化为正的电抗

    公开(公告)号：US4587500A

    公开(公告)日：1986-05-06

    申请号：US535962

    申请日：1983-09-23

    申请人： Kanji Tanaka ,  Kazuhisa Ishiguro

    发明人： Kanji Tanaka ,  Kazuhisa Ishiguro

    IPC分类号： H03B5/36 ,  H03H11/40 ,  H03H11/44 ,  H03H11/46 ,  H03H11/48 ,  H03H11/52

    CPC分类号： H03B5/366 ,  H03H11/48

    摘要： A variable reactance circuit which can produce equivalent reactance varying from negative given values to positive given values in accordance with fundamental reactance elements such as capacitor, coil, etc. The present invention has a big advantage of being capable of easily producing the positive, negative equivalent reactance given times as much as the basic reactance element with the use of a circuit which can be integrated.

    摘要翻译： 一种可变电抗电路，其可以根据诸如电容器，线圈等的基本电抗元件产生从负给定值到正给定值的等效电抗。本发明具有很大的优点，能够容易地产生正负等效 通过使用可以集成的电路，给出与基本电抗元件一样多的电抗。

    TUNING CIRCUIT AND RADIO RECEIVER USING THE SAME
    6.
    发明申请
    TUNING CIRCUIT AND RADIO RECEIVER USING THE SAME 审中-公开
    使用相同的调谐电路和无线电接收器

    公开(公告)号：US20090124225A1

    公开(公告)日：2009-05-14

    申请号：US12267272

    申请日：2008-11-07

    申请人： Kazuhisa Ishiguro ,  Yoshiaki Takahashi

    发明人： Kazuhisa Ishiguro ,  Yoshiaki Takahashi

    IPC分类号： H04B1/16 ,  H03H7/01

    CPC分类号： H03H7/42 ,  H03H2007/013

    摘要： In a tuning circuit constituted by connecting a coil L and two capacitors C1 and C2 into a π type, a total capacitance value obtained by adding respective capacitance values of an input capacitance Cin and the first capacitor C1 which are connected to one of terminals of a coil L is set to be equal to a capacitance value of the second capacitor C2 connected to the other terminal of the coil L (C2=Cin+C1). Consequently, a capacitance value on one terminal side of the coil L and a capacitance value on the other terminal side are set to be equal to each other and are thus balanced, and a level difference between two output signals on a parallel resonance point of the π type tuning circuit is reduced even if the capacitance values of the two capacitors C1 and C2 are decreased.

    摘要翻译： 在通过将线圈L和两个电容器C1和C2连接成pi型构成的调谐电路中，通过将输入电容Cin和第一电容器C1的相应电容值相加而获得的总电容值， 线圈L被设定为等于连接到线圈L的另一个端子（C2 = Cin + C1）的第二电容器C2的电容值。 因此，将线圈L的一个端子侧的电容值和另一方的端子侧的电容值设定为彼此相等，由此平衡，并且在平行谐振点上的两个输出信号之间的电平差 即使两个电容器C1和C2的电容值减小，pi型调谐电路也减小。

    Automatic gain control circuit
    7.
    发明授权
    Automatic gain control circuit 失效
    自动增益控制电路

    公开(公告)号：US08284876B2

    公开(公告)日：2012-10-09

    申请号：US12298358

    申请日：2006-11-29

    申请人： Kazuhisa Ishiguro

    发明人： Kazuhisa Ishiguro

    IPC分类号： H04L27/08 ,  H04B1/06

    CPC分类号： H03G3/3068

    摘要： There are provided an A/D converting circuit (10) for converting, into a digital signal, a broadband intermediate frequency signal which is output from a frequency converting circuit (5), and a DSP (11) for generating and outputting control data to control gains of an antenna damping circuit (3) and an LNA (4) based on a level of the broadband digital intermediate frequency signal which is output from the A/D converting circuit (10), and the broadband intermediate frequency signal which is output from the frequency converting circuit (5) is A/D converted and supplied to the DSP (11). Consequently, it is possible to reduce a frequency of a signal input to the A/D converting circuit (10). Thus, it is also possible to reduce a consumed current without requiring the use a special AD converter corresponding to a radio frequency input.

    摘要翻译： 提供了一种用于将从频率转换电路（5）输出的宽带中频信号转换为数字信号的A / D转换电路（10），以及用于生成并输出控制数据的DSP（11） 基于从A / D转换电路（10）输出的宽带数字中频信号的电平，输出天线阻尼电路（3）和LNA（4）的增益，以及输出的宽带中频信号 从频率转换电路（5）进行A / D转换并提供给DSP（11）。 因此，可以降低输入到A / D转换电路（10）的信号的频率。 因此，也可以在不需要使用与射频输入对应的专用AD转换器的情况下减少消耗电流。

    AUTOMATIC GAIN CONTROL CIRCUIT
    8.
    发明申请
    AUTOMATIC GAIN CONTROL CIRCUIT 审中-公开
    自动增益控制电路

    公开(公告)号：US20090310723A1

    公开(公告)日：2009-12-17

    申请号：US12306687

    申请日：2007-02-06

    申请人： Kazuhisa Ishiguro

    发明人： Kazuhisa Ishiguro

    IPC分类号： H04L27/08

    CPC分类号： H03G3/3052 ,  H04B1/109

    摘要： Circuits (an AGC amplifier 8 and a second A/D converting circuit 9) for detecting an antenna level of a disturbing wave are provided on an output of a frequency converting circuit 4, and levels of antenna ends of a desirable wave and the disturbing wave are calculated by a DSP 10 and a gain of an antenna damping circuit 2, an LNA 3 or the frequency converting circuit 4 is adjusted corresponding to the respective levels, thereby enabling an optimum gain distribution for an RF stage to be set corresponding to the levels of the desirable wave and the disturbing wave.

    摘要翻译： 用于检测干扰波的天线电平的电路（AGC放大器8和第二A / D转换电路9）设置在频率转换电路4的输出端上，并且期望的波和干扰波的天线端的电平 由DSP 10和天线阻尼电路2的增益计算，LNA 3或频率转换电路4根据各个电平进行调节，从而能够根据电平设定RF级的最佳增益分布 的理想波和干扰波。

    AUTOMATIC GAIN CONTROL CIRCUIT
    9.
    发明申请
    AUTOMATIC GAIN CONTROL CIRCUIT 失效
    自动增益控制电路

    公开(公告)号：US20090207952A1

    公开(公告)日：2009-08-20

    申请号：US12298358

    申请日：2006-11-29

    申请人： Kazuhisa Ishiguro

    发明人： Kazuhisa Ishiguro

    IPC分类号： H04L27/08

    CPC分类号： H03G3/3068

    摘要： There are provided an A/D converting circuit (10) for converting, into a digital signal, a broadband intermediate frequency signal which is output from a frequency converting circuit (5), and a DSP (11) for generating and outputting control data to control gains of an antenna damping circuit (3) and an LNA (4) based on a level of the broadband digital intermediate frequency signal which is output from the A/D converting circuit (10), and the broadband intermediate frequency signal which is output from the frequency converting circuit (5) is A/D converted and supplied to the DSP (11). Consequently, it is possible to reduce a frequency of a signal input to the A/D converting circuit (10). Thus, it is also possible to reduce a consumed current without requiring the use a special AD converter corresponding to a radio frequency input.

    摘要翻译： 提供了一种用于将从频率转换电路（5）输出的宽带中频信号转换为数字信号的A / D转换电路（10），以及用于生成并输出控制数据的DSP（11） 基于从A / D转换电路（10）输出的宽带数字中频信号的电平，输出天线阻尼电路（3）和LNA（4）的增益，以及输出的宽带中频信号 从频率转换电路（5）进行A / D转换并提供给DSP（11）。 因此，可以降低输入到A / D转换电路（10）的信号的频率。 因此，也可以在不需要使用与射频输入对应的专用AD转换器的情况下减少消耗电流。

    POWER AMPLIFIER AND ITS IDLING CURRENT SETTING CIRCUIT
    10.
    发明申请
    POWER AMPLIFIER AND ITS IDLING CURRENT SETTING CIRCUIT 失效
    功率放大器及其定义电流设置电路

    公开(公告)号：US20090115519A1

    公开(公告)日：2009-05-07

    申请号：US12092523

    申请日：2006-07-12

    申请人： Kazuhisa Ishiguro

    发明人： Kazuhisa Ishiguro

    IPC分类号： H03F3/45

    CPC分类号： H03F1/0261 ,  H03F1/308 ,  H03F3/301 ,  H03F3/3022 ,  H03F3/303 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2203/30061 ,  H03F2203/45596 ,  H03F2203/45726

    摘要： An idling current setting circuit (3) includes: current setting transistors (Q3, Q4) connected to output transistors (Q1, Q2) in a driver (2) in current mirror form; a plurality of current setting resistors (R1 to R4); and a plurality of switches (ASW1 to ASW4) for switching to any of the current setting resistors (R1 to R4). This enables the idling current to be set by the current mirror ratio between the current setting transistors (Q3, Q4) having no connection with the open gain of the power amplifier and the output transistors (Q1, Q2), so that the idling current can be arbitrarily set independently of the open gain.

    摘要翻译： 怠速电流设定电路（3）包括：以电流镜面形式连接到驱动器（2）中的输出晶体管（Q1，Q2）的电流设定晶体管（Q3，Q4） 多个电流设定电阻（R1〜R4）; 以及用于切换到任何电流设定电阻器（R1〜R4）的多个开关（ASW1〜ASW4）。 这使得能够通过与功率放大器和输出晶体管（Q1，Q2）的开放增益无关的电流设定晶体管（Q3，Q4）之间的电流镜比来设定怠速电流，使得空转电流可以 可以独立于开放增益任意设置。