公开(公告)号：US20240146254A1

公开(公告)日：2024-05-02

申请号：US18050338

申请日：2022-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ankur CHAUHAN ,  Orlando LAZARO ,  Kushal MURTHY ,  Andres BLANCO ,  Henry EDWARDS

IPC: H03F1/30 ,  H01L27/02

CPC classification number: H03F1/308 ,  H01L27/0211

Abstract: A power transistor includes an ambient temperature input, a local temperature sensor, an array of transistor cells, and a thermal feedback circuit. The ambient temperature input is configured to receive an ambient temperature signal that is representative of an ambient temperature of the power transistor. The array of transistor cells has a control input. The local temperature sensor is configured to provide a local temperature signal that is representative of a temperature of the array of transistor cells. The thermal feedback circuit is coupled to the ambient temperature input, the local temperature sensor, and the control input. The thermal feedback circuit is configured to modulate a control signal provided at the control input based on a difference between the ambient temperature signal and the local temperature signal.

公开(公告)号：US09705454B2

公开(公告)日：2017-07-11

申请号：US15207362

申请日：2016-07-11

Applicant: Marvell World Trade, Ltd.

Inventor： David M. Signoff ,  Ming He ,  Wayne A. Loeb

IPC: H03F1/32 ,  H03F3/24 ,  G05F1/46 ,  H03H7/01 ,  H03F1/30 ,  H03F3/26

CPC classification number: H03F3/245 ,  G05F1/46 ,  H03F1/301 ,  H03F1/308 ,  H03F3/195 ,  H03F3/265 ,  H03F3/505 ,  H03F2200/24 ,  H03F2200/451 ,  H03F2200/453 ,  H03F2200/534 ,  H03F2200/555 ,  H03F2200/69 ,  H03H7/0107

Abstract: A circuit includes a bias circuit for a biased transistor. The bias circuit includes a master-slave source follower circuit, a reference transistor, and a bias circuit voltage output coupled to the biased transistor and configured to provide a bias voltage. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. A signal ground circuit may be coupled between the biased transistor and one or more components of the bias circuit that do not generate significant return currents to a power supply ground. A method includes generating a current in a reference transistor according to a first voltage generated using a master source follower circuit, generating a second voltage substantially identical to the first voltage using a slave source follower circuit, and providing the second voltage to a biased transistor. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor.

公开(公告)号：US09455675B2

公开(公告)日：2016-09-27

申请号：US14554001

申请日：2014-11-25

Applicant: Beken Corporation

Inventor： Ronghui Kong ,  Dawei Guo

IPC: H03F3/04 ,  H03F3/30 ,  H03F1/30 ,  H03K3/3565

CPC classification number: H03F3/3022 ,  H03F1/308 ,  H03F2200/135 ,  H03F2200/456 ,  H03F2200/555 ,  H03F2203/30031 ,  H03F2203/30078 ,  H03K3/3565

Abstract: An amplifier comprises a biasing unit, an amplifying unit and a Schmitt trigger. The biasing unit is configured to generate a bias current which is independent of the power supply, so as to increase power supply rejection ratio. The amplifying unit is connected to the biasing unit and configured to receive an input voltage and generate an amplified voltage based on the biasing current. The Schmitt trigger is connected to the amplifier and configured to generate and output a modified voltage.

Abstract translation: 放大器包括偏置单元，放大单元和施密特触发器。 偏压单元被配置为产生独立于电源的偏置电流，从而增加电源抑制比。 放大单元连接到偏置单元并且被配置为接收输入电压并且基于偏置电流产生放大的电压。 施密特触发器连接到放大器，并配置为产生和输出修改的电压。

公开(公告)号：US09407208B2

公开(公告)日：2016-08-02

申请号：US14535454

申请日：2014-11-07

Applicant: Lattice Semiconductor Corporation

Inventor： Vinh Ho ,  Carl Chai ,  Allan Lin

IPC: H03F3/26 ,  H03F1/02 ,  H03F3/21 ,  H03F3/45

CPC classification number: H03F1/0205 ,  H03F1/0261 ,  H03F1/304 ,  H03F1/308 ,  H03F3/21 ,  H03F3/211 ,  H03F3/26 ,  H03F3/3022 ,  H03F3/45076 ,  H03F3/45183 ,  H03F2200/129 ,  H03F2203/45332 ,  H03F2203/45512

Abstract: A Class AB amplifier has a control stage and a push-pull stage. The control stage has a programmable resistor that allows a floating constant voltage to applied to the push-pull stage such that the quiescent current of the amplifier is relatively low. The configuration enables the amplifier to operate properly at relatively low power-supply voltage levels. The amplifier can be configured as the output driver for an operational amplifier (op-amp) with a Miller compensation configuration that replaces the conventional Miller compensation resistor with a transistor that is part of the op-amp.

Abstract translation: AB类放大器具有控制级和推挽级。 控制级具有可编程电阻器，其允许浮动恒定电压施加到推挽级，使得放大器的静态电流相对较低。 该配置使放大器能够在相对较低的电源电压电平下正常工作。 放大器可以配置为具有米勒补偿配置的运算放大器（运算放大器）的输出驱动器，可以用作为运算放大器一部分的晶体管替代传统的米勒补偿电阻。

公开(公告)号：US20160134240A1

公开(公告)日：2016-05-12

申请号：US14818882

申请日：2015-08-05

Applicant: Texas Instruments Incorporated

Inventor： Harish Kundur Subramaniyan ,  Eric Klumperink ,  Venkatesh Srinivasan ,  Ali Kiaei ,  Bram Nauta

IPC: H03F1/02 ,  H03F1/32 ,  H03F3/193 ,  H03F1/30

CPC classification number: H03F3/193 ,  H03F1/0261 ,  H03F1/301 ,  H03F1/308 ,  H03F1/3205 ,  H03F1/3217 ,  H03F3/3022 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2203/30078 ,  H03F2203/30111

Abstract: Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transistor and first P-channel transistor are coupled to an output conductor. A first degeneration resistor is coupled between a source of the first P-channel transistor and a first supply voltage and a second degeneration resistor is coupled between a source of the first N-channel transistor and a second supply voltage. A first low impedance bypass circuit is coupled between the sources of the first P-channel transistor and the first N-channel transistor. A low impedance bypass circuit re-circulates second order distortion current that is induced by second-order distortion in drain currents of the first P-channel transistor and the first N-channel transistor, through the first N-channel transistor and first P-channel transistor.

Abstract translation: 在包括第一N沟道晶体管和第一P沟道晶体管的CMOS跨导电路中，三阶失真减小，第一N沟道晶体管和第一P沟道晶体管的栅极被耦合以接收输入信号。 第一N沟道晶体管和第一P沟道晶体管的漏极耦合到输出导体。 第一退化电阻器耦合在第一P沟道晶体管的源极和第一电源电压之间，而第二退化电阻耦合在第一N沟道晶体管的源极和第二电源电压之间。 第一低阻抗旁路电路耦合在第一P沟道晶体管和第一N沟道晶体管的源极之间。 低阻抗旁路电路通过第一N沟道晶体管和第一P沟道重新流过在第一P沟道晶体管和第一N沟道晶体管的漏极电流中由二阶失真引起的二阶失真电流 晶体管。

公开(公告)号：US20160118939A1

公开(公告)日：2016-04-28

申请号：US14554001

申请日：2014-11-25

Applicant: Beken Corporation

Inventor： Ronghui KONG ,  Dawei GUO

IPC: H03F1/02 ,  H03F3/04

CPC classification number: H03F3/3022 ,  H03F1/308 ,  H03F2200/135 ,  H03F2200/456 ,  H03F2200/555 ,  H03F2203/30031 ,  H03F2203/30078 ,  H03K3/3565

Abstract: An amplifier comprises a biasing unit, an amplifying unit and a Schmitt trigger. The biasing unit is configured to generate a bias current which is independent of the power supply, so as to increase power supply rejection ratio. The amplifying unit is connected to the biasing unit and configured to receive an input voltage and generate an amplified voltage based on the biasing current. The Schmitt trigger is connected to the amplifier and configured to generate and output a modified voltage.

Abstract translation: 放大器包括偏置单元，放大单元和施密特触发器。 偏压单元被配置为产生独立于电源的偏置电流，从而增加电源抑制比。 放大单元连接到偏置单元并且被配置为接收输入电压并且基于偏置电流产生放大的电压。 施密特触发器连接到放大器，并配置为产生和输出修改的电压。

公开(公告)号：US09225304B1

公开(公告)日：2015-12-29

申请号：US14522678

申请日：2014-10-24

Applicant: SanDisk 3D LLC

Inventor： Vincent Lai

IPC: H03F3/45 ,  H03F1/30

CPC classification number: H03F1/308 ,  G11C11/5642 ,  G11C27/005 ,  H03F3/3022 ,  H03F3/45183 ,  H03F3/45219 ,  H03F2200/45 ,  H03F2200/78 ,  H03F2203/30096 ,  H03F2203/30129 ,  H03F2203/45116

Abstract: A single-stage folded cascode buffer including an amplifier, a first analog comparator, a second analog comparator, a first transistor, and a second transistor, The amplifier includes a first input terminal, a second input terminal, and an output terminal coupled to the second input terminal of the amplifier. The first analog comparator includes a first input terminal, a second input terminal, and an output terminal. The second analog comparator includes a first input terminal, a second input terminal, and an output terminal. The first transistor includes a first terminal, a second terminal coupled to the output terminal of the first analog comparator, and a third terminal coupled to the output terminal of the amplifier. The second transistor includes a first terminal coupled to the output terminal of the amplifier, a second terminal coupled to the output terminal of the second analog comparator, and a third terminal.

Abstract translation: 包括放大器，第一模拟比较器，第二模拟比较器，第一晶体管和第二晶体管的单级折叠共源共栅缓冲器。放大器包括第一输入端子，第二输入端子和耦合到第二晶体管的输出端子 放大器的第二输入端。 第一模拟比较器包括第一输入端，第二输入端和输出端。 第二模拟比较器包括第一输入端，第二输入端和输出端。 第一晶体管包括第一端子，耦合到第一模拟比较器的输出端子的第二端子和耦合到放大器的输出端子的第三端子。 第二晶体管包括耦合到放大器的输出端的第一端子，耦合到第二模拟比较器的输出端的第二端子和第三端子。

公开(公告)号：US20150263679A1

公开(公告)日：2015-09-17

申请号：US14621133

申请日：2015-02-12

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Tetsuro ITAKURA ,  Masanori FURUTA

IPC: H03F1/26 ,  H03F3/16

CPC classification number: H03F3/3028 ,  H03F1/308 ,  H03F2200/291 ,  H03F2203/30084 ,  H03F2203/30117

Abstract: An inverting amplifier according to a first embodiment includes an inverter circuit, a first voltage generating circuit, and a second voltage generating circuit. The inverter circuit has an input terminal, an output terminal, a first first-conductivity transistor, and a first second-conductivity transistor. The first (second) voltage generating circuit has a first (second) current source, a second first (second)-conductivity transistor, and a third first (second)-conductivity transistor. The first (second) current source supplies a predetermined current. The second first (second)-conductivity transistor has a control terminal with a predetermined bias voltage applied, and two ends connected to the other end of the first first (second)-conductivity transistor and the first (second) current source, respectively. The third first (second)-conductivity transistor has a control terminal connected to the other end of the second first (second)-conductivity transistor, and one end connected to one end of the second first (second)-conductivity transistor.

Abstract translation: 根据第一实施例的反相放大器包括逆变器电路，第一电压产生电路和第二电压产生电路。 逆变器电路具有输入端子，输出端子，第一第一导电晶体管和第一第二导电晶体管。 第一（第二）电压产生电路具有第一（第二）电流源，第二第一（第二） - 导电晶体管和第三第一（第二） - 导电晶体管。 第一（第二）电流源提供预定电流。 第二第一（第二） - 导体晶体管具有施加预定偏置电压的控制端子，并且两端分别连接到第一第一（第二） - 导体晶体管和第一（第二）电流源的另一端。 第三第一（第二） - 导体晶体管具有连接到第二第一（第二） - 导体晶体管的另一端的控制端，并且一端连接到第二第一（第二） - 导体晶体管的一端。

公开(公告)号：US08405460B2

公开(公告)日：2013-03-26

申请号：US13044968

申请日：2011-03-10

Applicant: Ken Hunt

Inventor： Ken Hunt

IPC: H03F3/26

CPC classification number: H03F3/3028 ,  H03F1/308 ,  H03F2203/30021

Abstract: Integrated circuits with amplification circuitry are provided. The amplification circuitry may have an input terminal, an output terminal, a positive power supply terminal, and a ground terminal. The amplification circuitry may include first, second, and third stages. The first stage may provide biasing for the second stage. The second stage may provide biasing for the third stage. The second stage may provide paths for conveying an input signal from the input terminal to the third stage. The second stage may bias the amplifier to have low quiescent current and low shoot-through current. The second stage may prevent PVT variations such as supply voltage variations from affecting the quiescent current and shoot-through current of the amplifier. To increase the high-frequency response of the amplifier, capacitors may be added to the paths for conveying the input signal from the input terminal to the third stage.

Abstract translation: 提供具有放大电路的集成电路。 放大电路可以具有输入端子，输出端子，正电源端子和接地端子。 放大电路可以包括第一，第二和第三级。 第一阶段可以为第二阶段提供偏置。 第二阶段可以提供第三阶段的偏置。 第二级可以提供用于将输入信号从输入端传送到第三级的路径。 第二级可能会使放大器偏置为具有低静态电流和低直通电流。 第二级可以防止诸如电源电压变化的PVT变化影响放大器的静态电流和直通电流。 为了增加放大器的高频响应，可以将电容器添加到用于将输入信号从输入端子输送到第三级的路径。

公开(公告)号：US08279005B2

公开(公告)日：2012-10-02

申请号：US12593829

申请日：2008-03-18

Applicant: Johannes H. A. Brekelmans ,  Lorenzo Tripodi

Inventor： Johannes H. A. Brekelmans ,  Lorenzo Tripodi

IPC: H03F3/18

CPC classification number: H03F1/308 ,  H03F3/3022

Abstract: There is provided a method and apparatus for maintaining a bias current that flows through two transistors at a target level. The two transistors are both connected to form a series network between positive and negative voltage supply terminals. The bias current flows through the two transistors when the circuit is at equilibrium, and the threshold voltage of the transistors is controlled by controlling the voltage that is applied to the transistors bulk terminals. In addition to the two transistors, there is provided a control circuit that measures a circuit parameter that is indicative of the level of bias current flowing through the two transistors. In response to the measured parameter, the control circuit adjusts the bulk voltage levels of the two transistors so as to alter the transistors threshold voltages and maintain the level of bias current at a target level.

Abstract translation: 提供了一种用于维持在目标电平上流过两个晶体管的偏置电流的方法和装置。 两个晶体管都被连接以在正电压和负电压端子之间形成串联网络。 当电路处于平衡时，偏置电流流过两个晶体管，并且通过控制施加到晶体管体式端子的电压来控制晶体管的阈值电压。 除了两个晶体管之外，还提供了一种控制电路，其测量指示流经两个晶体管的偏置电流的电平的电路参数。 响应于测量的参数，控制电路调节两个晶体管的体电压电平，以便改变晶体管阈值电压并将偏置电流的电平维持在目标水平。