公开(公告)号：US5393995A

公开(公告)日：1995-02-28

申请号：US68162

申请日：1993-05-28

申请人： Tsutomu Nakagawa ,  Futoshi Tokunoh ,  Kouji Niinobu

发明人： Tsutomu Nakagawa ,  Futoshi Tokunoh ,  Kouji Niinobu

IPC分类号： H01L29/74

CPC分类号： H01L29/7416

摘要： There is disclosed a semiconductor device wherein a p layer (7) is formed in an isolating portion (Z) and portions (1a, 1b) of an n-type base layer (1) lie on opposite sides of the p layer (7), the upper surfaces of the p layer (7) and the portions (1a, 1b) lying in the same plane as the upper surface of a p layer (3). The presence of the p layer (7) provides for high resistance to breakdown and high formation accuracy of the p layers (2, 3, 7) as compared with a structure in which the isolating portion (Z) lies in the bottom of a the recess, whereby the semiconductor device is less susceptible to short-circuit between the p-type base layer (2) and the p layer (3).

摘要翻译： 公开了一种半导体器件，其中ap层（7）形成在隔离部分（Z）中，并且n型基极层（1）的部分（1a，1b）位于p层（7）的相对侧上， p层（7）的上表面和与ap层（3）的上表面位于同一平面中的部分（1a，1b）。 与隔离部分（Z）位于底部的结构相比，p层（7）的存在提供了p层（2,3,7）的高耐击穿性和高成形精度， 从而半导体器件不易受p型基极层（2）和p层（3）之间的短路影响。

公开(公告)号：US5574297A

公开(公告)日：1996-11-12

申请号：US407650

申请日：1995-03-21

申请人： Nozomu Sennenbara ,  Kouji Niinobu ,  Kazuhiko Niwayama ,  Futoshi Tokunoh

发明人： Nozomu Sennenbara ,  Kouji Niinobu ,  Kazuhiko Niwayama ,  Futoshi Tokunoh

IPC分类号： H01L29/74 ,  H01L29/08 ,  H01L29/417 ,  H01L29/744 ,  H01L31/111

CPC分类号： H01L29/744 ,  H01L24/06 ,  H01L29/0834 ,  H01L29/41716 ,  H01L2924/1301

摘要： In order to compatibly implement improvement in withstand voltage and ON-state resistance as well as reduction in turnon loss and improvement in di/dt resistance, an n buffer layer (12) is locally exposed on a lower surface of a semiconductor substrate (160), while a polysilicon additional resistive layer (104) is formed to cover the exposed surface. An anode electrode (101) covering the lower surface of the semiconductor substrate (160) is connected to a p emitter layer (11) and the additional resistive layer (104). Thus, the n buffer layer (12) and the anode electrode (101) are connected with each other through the additional resistive layer (104), whereby a gate trigger current is reduced. Thus, turnon loss is reduced and di/dt resistance is increased. At the same time, the withstand voltage and the ON-state resistance are excellent due to provision of the n buffer layer (12). Thus, the turnon loss is reduced and the di/dt resistance is improved without deteriorating the withstand voltage and the ON-state resistance.

摘要翻译： 为了兼容地实现耐压和导通电阻的改善以及降低漏电损耗和改善di / dt电阻，在半导体衬底（160）的下表面上局部露出n缓冲层（12） ，同时形成多晶硅附加电阻层（104）以覆盖暴露的表面。 覆盖半导体衬底（160）的下表面的阳极电极（101）连接到p发射极层（11）和附加电阻层（104）。 因此，n缓冲层（12）和阳极电极（101）通过附加电阻层（104）彼此连接，从而减小了栅极触发电流。 因此，导通损失减小，di / dt电阻增加。 同时，由于提供n缓冲层（12），耐压和导通电阻极好。 因此，在不降低耐压和导通电阻的情况下，螺线管损耗减小，di / dt电阻提高。