公开(公告)号：US20180204913A1

公开(公告)日：2018-07-19

申请号：US15918581

申请日：2018-03-12

申请人： ABB Schweiz AG

发明人： Martin Arnold ,  Umamaheswara Vemulapati

IPC分类号： H01L29/10 ,  H01L29/745 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/1066 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0839 ,  H01L29/102 ,  H01L29/36 ,  H01L29/41716 ,  H01L29/66363 ,  H01L29/66393 ,  H01L29/744 ,  H01L29/745

摘要： The invention relates to a turn-off power semiconductor device comprising a plurality of thyristor cells, each thyristor cell comprising a cathode region; a base layer; a drift layer; an anode layer; a gate electrode which is arranged lateral to the cathode region in contact with the base layer; a cathode electrode; and an anode electrode. Interfaces between the cathode regions and the cathode electrodes as well as interfaces between the base layers and the gate electrodes of the plurality of thyristor cells are flat and coplanar. In addition, the base layer includes a gate well region extending from its contact with the gate electrode to a depth, which is at least half of the depth of the cathode region, wherein, for any depth, the minimum doping concentration of the gate well region at this depth is 50% above a doping concentration of the base layer between the cathode region and the gate well region at this depth and at a lateral position, which has in an orthogonal projection onto a plane parallel to the first main side a distance of 2 μm from the cathode region. The base layer includes a compensated region of the second conductivity type, the compensated region being arranged directly adjacent to the first main side and between the cathode region and the gate well region, wherein the density of first conductivity type impurities relative to the net doping concentration in the compensated region is at least 0.4.

公开(公告)号：US20180053663A1

公开(公告)日：2018-02-22

申请号：US15677091

申请日：2017-08-15

申请人： Infineon Technologies AG

发明人： Mathias Plappert ,  Stefan Krivec ,  Andreas Riegler ,  Karin Schrettlinger

IPC分类号： H01L21/3215 ,  H01L23/29 ,  H01L29/739 ,  H01L29/66 ,  H01L29/06 ,  H01L23/31

CPC分类号： H01L21/32155 ,  H01L21/76886 ,  H01L23/293 ,  H01L23/298 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L29/0619 ,  H01L29/401 ,  H01L29/417 ,  H01L29/41716 ,  H01L29/66325 ,  H01L29/7393 ,  H01L29/7436

摘要： In various embodiments, a method is provided. The method includes forming a metallization layer above at least one first region of a substrate. After forming the metallization layer at least one second region of the substrate is free of the metallization layer. The method further includes forming a barrier layer above the at least one first region of the substrate and above the at least one second region of the substrate. The barrier layer in the at least one first region of the substrate directly adjoins the metallization layer. The method further includes removing the barrier layer in the at least one first region of the substrate by drive-in of the barrier layer into the metallization layer.

公开(公告)号：US20160308024A1

公开(公告)日：2016-10-20

申请号：US15196776

申请日：2016-06-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： King-Yuen Wong ,  Chen-Ju Yu ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen ,  Fu-Wei Yao ,  Fu-Chih Yang

IPC分类号： H01L29/66 ,  H01L21/266 ,  H01L21/28 ,  H01L29/417 ,  H01L21/3065 ,  H01L21/311 ,  H01L29/20 ,  H01L29/423 ,  H01L21/265 ,  H01L29/778

CPC分类号： H01L29/66462 ,  H01L21/26546 ,  H01L21/266 ,  H01L21/28264 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/41716 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/66621 ,  H01L29/7786 ,  H01L29/7787

摘要： An integrated circuit device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a gate dielectric over the second III-V compound layer, and a gate electrode over the gate dielectric. An anode electrode and a cathode electrode are formed on opposite sides of the gate electrode. The anode electrode is electrically connected to the gate electrode. The anode electrode, the cathode electrode, and the gate electrode form portions of a rectifier.

公开(公告)号：US20160204240A1

公开(公告)日：2016-07-14

申请号：US15075766

申请日：2016-03-21

申请人： ABB Technology AG

发明人： Friedhelm Bauer

IPC分类号： H01L29/745 ,  H01L29/417 ,  H01L29/10 ,  H01L29/08

CPC分类号： H01L29/7455 ,  H01L29/0649 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/0847 ,  H01L29/1012 ,  H01L29/1095 ,  H01L29/41716 ,  H01L29/749

摘要： A power semiconductor device is provided comprising: a collector electrode, a collector layer of a second conductivity type, a drift layer of a first conductivity type, a base layer of the second conductivity type, a first insulating layer having an opening, an emitter layer of the first conductivity type, the emitter layer contacts the base layer and separated from the drift layer by one of the first insulating layer or the base layer, a body layer of the second conductivity type arranged laterally to the emitter layer and separated from the base layer by the first insulating layer and the emitter layer, a source region of the first conductivity type separated from the emitter layer by the body layer, an emitter electrode contacted by the source region. The device further comprises a first layer of the second conductivity type contacting the emitter electrode and separated from the base layer, and a second layer of the first conductivity type arranged between the first layer and the base layer and separated from the emitter layer and the source region. A planar MIS gate electrode is arranged laterally from the emitter electrode, a corresponding MIS channel being formable between the source region, the body layer and the emitter layer. A thyristor current path extends between the emitter layer, the base layer and the drift layer through the opening, and a turn-off MIS channel is formable below the planar MIS gate electrode from the first layer, the second layer, the base layer to the drift layer.

摘要翻译： 提供了一种功率半导体器件，包括：集电极电极，第二导电类型的集电极层，第一导电类型的漂移层，第二导电类型的基极层，具有开口的第一绝缘层，发射极层 所述第一导电类型的发射极层与所述基极层接触并且通过所述第一绝缘层或所述基底层之一与所述漂移层分离，所述第二导电类型的主体层横向排列到所述发射极层并与所述基极分离 通过第一绝缘层和发射极层，由主体层与发射极层分离的第一导电类型的源极区域，与源极区域接触的发射极。 该器件还包括第二导电类型的第一层与第二导电类型接触，并与基极层分离，并且第一导电类型的第二层布置在第一层与基极层之间，并与发射极层和源极 地区。 平面MIS栅极电极从发射极侧向设置，相应的MIS沟道可在源极区域，主体层和发射极层之间形成。 晶闸管电流路径通过开口在发射极层，基极层和漂移层之间延伸，并且在第一层，第二层，基底层到第二层 漂移层。

公开(公告)号：US20140264365A1

公开(公告)日：2014-09-18

申请号：US14144716

申请日：2013-12-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： King-Yuen Wong ,  Chen-Ju Yu ,  Jiun-Lei Jerry Yu ,  Po-Chih Chen ,  Fu-Wei Yao ,  Fu-Chih Yang

IPC分类号： H01L29/66 ,  H01L29/20 ,  H01L29/778

CPC分类号： H01L29/66462 ,  H01L21/26546 ,  H01L21/266 ,  H01L21/28264 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/41716 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/66621 ,  H01L29/7786 ,  H01L29/7787

摘要： An integrated circuit device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a gate dielectric over the second III-V compound layer, and a gate electrode over the gate dielectric. An anode electrode and a cathode electrode are formed on opposite sides of the gate electrode. The anode electrode is electrically connected to the gate electrode. The anode electrode, the cathode electrode, and the gate electrode form portions of a rectifier.

摘要翻译： 集成电路器件包括第一III-V化合物层，第一III-V化合物层上的第二III-V化合物层，第二III-V化合物层上的栅极电介质，以及栅极电介质上的栅电极。 阳极电极和阴极电极形成在栅电极的相对侧上。 阳极电极与栅电极电连接。 阳极电极，阴极电极和栅电极形成整流器的部分。

公开(公告)号：US07915678B1

公开(公告)日：2011-03-29

申请号：US11155081

申请日：2005-06-17

申请人： Vladislav Vashchenko

发明人： Vladislav Vashchenko

IPC分类号： H01L29/72

CPC分类号： H01L29/7436 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/41716 ,  H01L29/4238 ,  H01L29/7816

摘要： In an NLDMOS, DMOS and NMOS device, the ability is provided for withstanding snapback conditions by providing one or more p+ emitter regions interdigitated between drain regions having drain contacts and electrically connecting the drain contacts to contacts of the emitter regions.

摘要翻译： 在NLDMOS，DMOS和NMOS器件中，通过提供在具有漏极触点的漏极区域之间交叉指向并且将漏极触点电连接到发射极区域的触点的一个或多个p +发射极区域，提供了抵抗突发状态的能力。

公开(公告)号：US07049182B1

公开(公告)日：2006-05-23

申请号：US10682283

申请日：2003-10-09

申请人： Andrew Horch ,  Scott Robins

发明人： Andrew Horch ,  Scott Robins

IPC分类号： H01L21/332

CPC分类号： H01L29/41716 ,  Y10S977/70

摘要： A semiconductor device is formed having a thyristor, a pass device and a conductive shunt that electrically connects an emitter region of the thyristor with a node near an upper surface of the substrate. In one example embodiment of the present invention, the conductive shunt is formed in a trench in a substrate and extending from an upper surface of the substrate to an emitter region of a vertical thyristor, with the emitter region being in the substrate and below the upper surface. In one implementation, the thyristor includes a thyristor body and a control port, with an N+ emitter region of the thyristor body being in the substrate and below and upper surface thereof. A pass device is formed adjacent to the thyristor, and the conductive shunt is formed in a trench extending from the N+ emitter region to a source/drain region of the pass device. With this approach, thyristor applications can be implemented having an emitter region in a substrate and not necessarily directly accessible, for example, via an upper surface of the substrate. This approach is also useful, for example, in applications where a cathode-down thyristor is used, such as when it is desirable to form the thyristor control port near a bottom portion of the thyristor, and in high-density circuit applications, such as memory arrays.

摘要翻译： 形成半导体器件，其具有将晶闸管的发射极区域与衬底的上表面附近的节点电连接的晶闸管，通过器件和导电分流器。 在本发明的一个示例实施例中，导电分流器形成在衬底中的沟槽中并且从衬底的上表面延伸到垂直晶闸管的发射极区域，其中发射极区域在衬底中并且在上部 表面。 在一个实施方案中，晶闸管包括晶闸管主体和控制端口，晶闸管主体的N +发射极区域位于衬底中并且其下表面和上表面。 形成与晶闸管相邻的通过器件，并且导电分流器形成在从N +发射极区域延伸到通过器件的源极/漏极区域的沟槽中。 利用这种方法，可以实现晶闸管应用，其在衬底中具有发射极区域，并且不一定直接可访问，例如经由衬底的上表面。 这种方法在例如使用阴极 - 下降晶闸管的应用中也是有用的，例如当期望在晶闸管的底部附近形成晶闸管控制端口时，以及在高密度电路应用中，例如 存储器阵列。

公开(公告)号：US06888176B1

公开(公告)日：2005-05-03

申请号：US10609185

申请日：2003-06-26

申请人： Andrew E. Horch ,  Fred Hause

发明人： Andrew E. Horch ,  Fred Hause

IPC分类号： H01L21/332 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/66393 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41716 ,  H01L29/7436

摘要： In a method of processing a semiconductor device, a silicide-blocking layer may be formed over a semiconductor material. After defining the silicide-blocking layer, impurities may be implanted into portions of the semiconductor material as defined by the silicide-blocking layer. After the implant, silicide may be formed in a surface region of the semiconductor material as permitted by the silicide-blocking layer. Regions of the impurity implant may comprise boundaries that are related to the outline of the silicide formed thereover. In a further embodiment, the implant may define a base region to a thyristor device. The implant may be performed with an angle of incidence to extend portions of the base region beneath a peripheral edge of the blocking mask. Next, an anode-emitter region may be formed using an implant of a substantially orthogonal angle of incidence and self-aligned to the mask. Epitaxial material may then be formed selectively over exposed regions of the semiconductor material as defined by the silicide-blocking mask. Silicide might also be formed after select exposed regions as defined by the silicide-blocking mask. The silicide-blocking mask may thus be used for alignment of implants, and also for defining epitaxial and silicide alignments.

摘要翻译： 在半导体器件的处理方法中，可以在半导体材料上形成硅化物阻挡层。 在限定硅化物阻挡层之后，可以将杂质注入半导体材料的部分，如由硅化物阻挡层所限定的。 在植入之后，硅化物可以形成在半导体材料的表面区域，如硅化物阻挡层所允许的。 杂质植入物的区域可以包括与其上形成的硅化物的轮廓相关的边界。 在另一实施例中，植入物可以限定到晶闸管器件的基极区域。 可以以入射角来执行植入物，以将阻挡掩模的外围边缘下方的基底区域的部分延伸。 接下来，可以使用基本上正交的入射角并与掩模自对准的植入物形成阳极 - 发射极区域。 然后可以在由硅化物阻挡掩模限定的半导体材料的暴露区域上选择性地形成外延材料。 也可以在由硅化物阻挡掩模定义的选择的暴露区域之后形成硅化物。 硅化物阻挡掩模因此可用于植入物的对准，并且还用于限定外延和硅化物对准。

公开(公告)号：US20050082565A1

公开(公告)日：2005-04-21

申请号：US10963383

申请日：2004-10-12

申请人： Samuel Menard ,  Christophe Mauriac

发明人： Samuel Menard ,  Christophe Mauriac

IPC分类号： H01L29/417 ,  H01L29/423 ,  H01L29/74 ,  H03K17/722 ,  H01L31/062

CPC分类号： H01L29/42308 ,  H01L29/41716 ,  H01L29/7408 ,  H03K17/722

摘要： A vertical SCR switch to be controlled by a high-frequency signal having at least four main alternated layers. The switch includes a gate terminal and a gate reference terminal connected via integrated capacitors to corresponding areas. In the case of a thyristor, having on its front surface side a main P-type semiconductor area formed in an N-type gate semiconductor area, a first portion of the main area being connected to one of the main areas, a second portion of the main area is connected to one of the control terminals via a first integrated capacitor, and a portion of the gate area being connected to the other of the control terminals via a second integrated capacitor.

摘要翻译： 垂直SCR开关由具有至少四个主交替层的高频信号控制。 该开关包括通过集成电容器连接到相应区域的栅极端子和栅极参考端子。 在晶闸管的情况下，在其正面侧具有形成在N型栅极半导体区域中的主P型半导体区域，主区域的第一部分连接到主区域之一，第二部分 主区域经由第一集成电容器连接到控制端子之一，并且栅极区域的一部分经由第二集成电容器连接到另一个控制端子。

公开(公告)号：US20050012112A1

公开(公告)日：2005-01-20

申请号：US10883973

申请日：2004-07-06

申请人： Yoshinori Murakami

发明人： Yoshinori Murakami

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L23/495 ,  H01L23/498 ,  H01L29/417 ,  H01L29/74

CPC分类号： H01L23/49861 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L29/41716 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/16152 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device wiring structure is provided to reduce the wiring inductance and curtail the generation of interfering electromagnetic waves. A semiconductor chip having an anode electrode and a cathode electrode provided on two oppositely-facing main surfaces is sandwiched between a sheet-shaped anode wiring and a sheet-shaped cathode wiring. The anode and cathode electrodes of the semiconductor chip are connected to the anode and the cathode wirings, respectively, arranged such that the electric currents flowing there-through flow in opposite directions. A conductive substrate having a main surface with a larger width than the cathode wiring is disposed adjacent to the anode wiring. The edges of the cathode wiring protrude beyond the edges of both the anode wiring and the semiconductor chip in all locations and the dimension of the protrusion is at least one half of the distance from the edge of the cathode wiring to the metal substrate.

摘要翻译： 提供半导体器件布线结构以减少布线电感并减少干扰电磁波的产生。 具有设置在两个相对的主表面上的阳极电极和阴极的半导体芯片被夹在片状阳极布线和片状阴极布线之间。 半导体芯片的阳极和阴极电极分别连接到阳极和阴极布线，使得流过其中的电流沿相反方向流动。 具有与阴极布线相比宽度大的主表面的导电基板邻近阳极布线设置。 阴极配线的边缘在所有位置突出超过阳极布线和半导体芯片的边缘，并且突起的尺寸距离阴极布线的边缘至金属基板的距离的至少一半。