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公开(公告)号:US20110128847A1
公开(公告)日:2011-06-02
申请号:US12954994
申请日:2010-11-29
申请人: Tsutomu Noguchi , Katsumi Imamura , Hideyo Fukunaga , Yoko Ohta , Yoshito Kachita , Naoya Matsusue
发明人: Tsutomu Noguchi , Katsumi Imamura , Hideyo Fukunaga , Yoko Ohta , Yoshito Kachita , Naoya Matsusue
IPC分类号: H04L12/26
CPC分类号: H04L47/52 , H04L47/10 , H04L47/215
摘要: The packet transmission device including: a first and a second storage module to store a token value; a token controller to add a predetermined token value to a first total token value, and subtract a predetermined token value from the first total value in response to the output of the packet; an overrun state controller to add an excess of the first total token value over a predetermined upper limit value to a second total token value, in the case where the first total token value added by addition control is greater than or equal to the predetermined upper limit value; and an underrun state controller to subtract a predetermined token value from the second total token value and add the subtracted token value to the first total token value, in the case where the subtracted first total token value is less than the predetermined upper limit value.
摘要翻译: 所述分组传输装置包括:存储令牌值的第一和第二存储模块; 令牌控制器,用于将预定的令牌值添加到第一总令牌值,并且响应于所述分组的输出从所述第一总值中减去预定的令牌值; 超额状态控制器,在通过相加控制添加的第一总令牌值大于或等于预定上限的情况下,将超过预定上限值的超过第一总令牌值添加到第二总令牌值 值; 以及欠运行状态控制器,用于从所述第二总令牌值中减去预定的令牌值,并且在减去的所述第一总令牌值小于所述预定上限值的情况下将所述减去的令牌值加到所述第一总令牌值。
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公开(公告)号:US08599693B2
公开(公告)日:2013-12-03
申请号:US12954994
申请日:2010-11-29
申请人: Tsutomu Noguchi , Katsumi Imamura , Hideyo Fukunaga , Yoko Ohta , Yoshito Kachita , Naoya Matsusue
发明人: Tsutomu Noguchi , Katsumi Imamura , Hideyo Fukunaga , Yoko Ohta , Yoshito Kachita , Naoya Matsusue
IPC分类号: G01R31/08
CPC分类号: H04L47/52 , H04L47/10 , H04L47/215
摘要: The packet transmission device including: a first and a second storage module to store a token value; a token controller to add a predetermined token value to a first total token value, and subtract a predetermined token value from the first total value in response to the output of the packet; an overrun state controller to add an excess of the first total token value over a predetermined upper limit value to a second total token value, in the case where the first total token value added by addition control is greater than or equal to the predetermined upper limit value; and an underrun state controller to subtract a predetermined token value from the second total token value and add the subtracted token value to the first total token value, in the case where the subtracted first total token value is less than the predetermined upper limit value.
摘要翻译: 所述分组传输装置包括:存储令牌值的第一和第二存储模块; 令牌控制器,用于将预定的令牌值添加到第一总令牌值,并且响应于所述分组的输出从所述第一总值中减去预定的令牌值; 超额状态控制器,在通过相加控制添加的第一总令牌值大于或等于预定上限的情况下,将超过预定上限值的超过第一总令牌值添加到第二总令牌值 值; 以及欠运行状态控制器,用于从所述第二总令牌值中减去预定的令牌值,并且在减去的所述第一总令牌值小于所述预定上限值的情况下将所述减去的令牌值加到所述第一总令牌值。
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3.
公开(公告)号:US20120079310A1
公开(公告)日:2012-03-29
申请号:US13209006
申请日:2011-08-12
申请人: Naoya Matsusue , Kanta Yamamoto
发明人: Naoya Matsusue , Kanta Yamamoto
IPC分类号: G06F1/12
CPC分类号: G06F1/14 , H04J3/0697
摘要: An interface board includes a synchronizer that synchronizes a first time that is a time of the interface board to a base time based on a master synchronization signal that is supplied by an external master time source and that defines the base time. The interface board also includes a comparator that compares a phase of a first synchronization signal that synchronizes to the first time with a phase of a shared synchronization signal sent by an interface controller that controls the interface board, and a notifier that notifies another interface board of a comparison result of the comparator.
摘要翻译: 接口板包括同步器,其基于由外部主时间源提供并定义基准时间的主同步信号,将接口板的第一时间与基准时间同步。 接口板还包括比较器,其将与第一次同步的第一同步信号的相位与控制接口板的接口控制器发送的共享同步信号的相位进行比较;以及通知器,其通知另一接口板 比较结果比较。
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4.
公开(公告)号:US08689035B2
公开(公告)日:2014-04-01
申请号:US13209006
申请日:2011-08-12
申请人: Naoya Matsusue , Kanta Yamamoto
发明人: Naoya Matsusue , Kanta Yamamoto
IPC分类号: G06F1/12 , H03K19/00 , H03L7/00 , H03B5/08 , H04B7/212 , H04J3/06 , H04L7/00 , G06F15/16 , G06F3/00 , G06F13/42
CPC分类号: G06F1/14 , H04J3/0697
摘要: An interface board includes a synchronizer that synchronizes a first time that is a time of the interface board to a base time based on a master synchronization signal that is supplied by an external master time source and that defines the base time. The interface board also includes a comparator that compares a phase of a first synchronization signal that synchronizes to the first time with a phase of a shared synchronization signal sent by an interface controller that controls the interface board, and a notifier that notifies another interface board of a comparison result of the comparator.
摘要翻译: 接口板包括同步器,其基于由外部主时间源提供并定义基准时间的主同步信号,将接口板的第一时间与基准时间同步。 接口板还包括比较器,其将与第一次同步的第一同步信号的相位与控制接口板的接口控制器发送的共享同步信号的相位进行比较;以及通知器,其通知另一接口板 比较结果比较。
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