公开(公告)号：US08599693B2

公开(公告)日：2013-12-03

申请号：US12954994

申请日：2010-11-29

Applicant: Tsutomu Noguchi ,  Katsumi Imamura ,  Hideyo Fukunaga ,  Yoko Ohta ,  Yoshito Kachita ,  Naoya Matsusue

Inventor： Tsutomu Noguchi ,  Katsumi Imamura ,  Hideyo Fukunaga ,  Yoko Ohta ,  Yoshito Kachita ,  Naoya Matsusue

IPC: G01R31/08

CPC classification number: H04L47/52 ,  H04L47/10 ,  H04L47/215

Abstract: The packet transmission device including: a first and a second storage module to store a token value; a token controller to add a predetermined token value to a first total token value, and subtract a predetermined token value from the first total value in response to the output of the packet; an overrun state controller to add an excess of the first total token value over a predetermined upper limit value to a second total token value, in the case where the first total token value added by addition control is greater than or equal to the predetermined upper limit value; and an underrun state controller to subtract a predetermined token value from the second total token value and add the subtracted token value to the first total token value, in the case where the subtracted first total token value is less than the predetermined upper limit value.

Abstract translation: 所述分组传输装置包括：存储令牌值的第一和第二存储模块; 令牌控制器，用于将预定的令牌值添加到第一总令牌值，并且响应于所述分组的输出从所述第一总值中减去预定的令牌值; 超额状态控制器，在通过相加控制添加的第一总令牌值大于或等于预定上限的情况下，将超过预定上限值的超过第一总令牌值添加到第二总令牌值 值; 以及欠运行状态控制器，用于从所述第二总令牌值中减去预定的令牌值，并且在减去的所述第一总令牌值小于所述预定上限值的情况下将所述减去的令牌值加到所述第一总令牌值。

公开(公告)号：US20100082864A1

公开(公告)日：2010-04-01

申请号：US12507872

申请日：2009-07-23

Applicant: Takeshi Sumou ,  Katsumi Imamura ,  Hideyo Fukunaga

Inventor： Takeshi Sumou ,  Katsumi Imamura ,  Hideyo Fukunaga

IPC: G06F13/00

CPC classification number: G06F13/4286

Abstract: An aspect of the embodiment utilizes a selection circuit that includes a first storage circuit for storing information of m×n bits each corresponding to a choice. The storage circuit indicates whether the corresponding choice is in a selectable state or not. A first round robin circuit for executing a round robin process on the second storage circuit selects one of the bits contained in the corresponding bit string and indicates that a choice is in a selectable state. A second round robin circuit executes the round robin process on the bit string having the m-bit width to select one of the bits indicating that the corresponding choice, and a control circuit controls the first and the second round robin circuit.

Abstract translation: 本实施例的一个方面利用了选择电路，其包括用于存储每个对应于选择的m×n位的信息的第一存储电路。 存储电路指示相应的选择是否处于可选状态。 用于在第二存储电路上执行循环处理的第一循环电路选择包含在相应位串中的一个位，并指示选择处于可选状态。 第二循环电路对具有m位宽的位串执行循环处理，以选择表示相应选择的位之一，并且控制电路控制第一和第二循环电路。

公开(公告)号：US20110128847A1

公开(公告)日：2011-06-02

申请号：US12954994

申请日：2010-11-29

Applicant: Tsutomu Noguchi ,  Katsumi Imamura ,  Hideyo Fukunaga ,  Yoko Ohta ,  Yoshito Kachita ,  Naoya Matsusue

Inventor： Tsutomu Noguchi ,  Katsumi Imamura ,  Hideyo Fukunaga ,  Yoko Ohta ,  Yoshito Kachita ,  Naoya Matsusue

IPC: H04L12/26

CPC classification number: H04L47/52 ,  H04L47/10 ,  H04L47/215

Abstract: The packet transmission device including: a first and a second storage module to store a token value; a token controller to add a predetermined token value to a first total token value, and subtract a predetermined token value from the first total value in response to the output of the packet; an overrun state controller to add an excess of the first total token value over a predetermined upper limit value to a second total token value, in the case where the first total token value added by addition control is greater than or equal to the predetermined upper limit value; and an underrun state controller to subtract a predetermined token value from the second total token value and add the subtracted token value to the first total token value, in the case where the subtracted first total token value is less than the predetermined upper limit value.

Abstract translation: 所述分组传输装置包括：存储令牌值的第一和第二存储模块; 令牌控制器，用于将预定的令牌值添加到第一总令牌值，并且响应于所述分组的输出从所述第一总值中减去预定的令牌值; 超额状态控制器，在通过相加控制添加的第一总令牌值大于或等于预定上限的情况下，将超过预定上限值的超过第一总令牌值添加到第二总令牌值 值; 以及欠运行状态控制器，用于从所述第二总令牌值中减去预定的令牌值，并且在减去的所述第一总令牌值小于所述预定上限值的情况下将所述减去的令牌值加到所述第一总令牌值。

公开(公告)号：US07103043B2

公开(公告)日：2006-09-05

申请号：US10078944

申请日：2002-02-19

Applicant: Yasushi Kurokawa ,  Hideyo Fukunaga ,  Takashi Maemoto ,  Yuuki Okumura

Inventor： Yasushi Kurokawa ,  Hideyo Fukunaga ,  Takashi Maemoto ,  Yuuki Okumura

IPC: H04L12/28 ,  H04L12/56

CPC classification number: H04L49/901 ,  H04L45/16 ,  H04L47/15 ,  H04L47/2441 ,  H04L47/50 ,  H04L49/9036

Abstract: The present invention is directed to the provision of a packet transmission apparatus and, more particularly, to a packet transmission apparatus achieving high-speed processing capability and enhanced relay quality for multicast packets. The packet transmission apparatus comprises: a non-copy packet arbiter which selects one of the non-copy packets by a prescribed algorithm, and requests transmission of the selected non-copy packet; a copy packet arbiter which selects one of the copy packets by a prescribed algorithm, and requests transmission of the selected copy packet; and a final arbiter which selects either one of the transmit requests, the transmit request from the non-copy packet arbiter or the transmit request from the copy packet arbiter, by a prescribed algorithm, and requests transmission of the selected packet, and wherein: the packet transmission apparatus transmits the packet requested by the final arbiter for transmission.

公开(公告)号：US07496034B2

公开(公告)日：2009-02-24

申请号：US11077868

申请日：2005-03-11

Applicant: Hideyo Fukunaga ,  Katsumi Imamura ,  Yasushi Kurokawa ,  Hideyuki Kudou ,  Yoko Watanabe

Inventor： Hideyo Fukunaga ,  Katsumi Imamura ,  Yasushi Kurokawa ,  Hideyuki Kudou ,  Yoko Watanabe

IPC: H04L12/56

CPC classification number: H04L47/6215 ,  H04L47/50

Abstract: A packet transmission device improved in packet transmission efficiency. Each packet input processor generates a pointer and identifies a packet type with respect to a received packet, and generates identification data including the pointer and the packet type identification result. A memory access controller detects a header readout amount of the packet based on the packet type identification result, generates first readout data including the header readout amount and a readout pointer indicative of a storage location of the packet in a shared memory, and adaptively reads out header data of the packet from the shared memory in accordance with the first readout data. A protocol processor analyzes the destination of the read header data, and a packet updater updates the old destination address of the packet to a new one to generate a packet with the updated destination address, and outputs the generated packet.

Abstract translation: 分组传输设备提高了分组传输效率。 每个分组输入处理器产生指针并且相对于接收到的分组标识分组类型，并且生成包括指针和分组类型识别结果的标识数据。 存储器访问控制器基于分组类型识别结果来检测分组的报头读出量，产生包括报头读出量的第一读出数据和表示分组在共享存储器中的存储位置的读出指针，并自适应地读出 根据第一读出数据来自共享存储器的分组的报头数据。 协议处理器分析读取标题数据的目的地，并且分组更新器将分组的旧目的地地址更新为新的分组，以生成具有更新的目的地地址的分组，并输出生成的分组。

公开(公告)号：US08032677B2

公开(公告)日：2011-10-04

申请号：US12507872

申请日：2009-07-23

Applicant: Takeshi Sumou ,  Katsumi Imamura ,  Hideyo Fukunaga

Inventor： Takeshi Sumou ,  Katsumi Imamura ,  Hideyo Fukunaga

IPC: G06F13/26

CPC classification number: G06F13/4286

Abstract: An aspect of the embodiment utilizes a selection circuit that includes a first storage circuit for storing information of m×n bits each corresponding to a choice. The storage circuit indicates whether the corresponding choice is in a selectable state or not. A first round robin circuit for executing a round robin process on the second storage circuit selects one of the bits contained in the corresponding bit string and indicates that a choice is in a selectable state. A second round robin circuit executes the round robin process on the bit string having the m-bit width to select one of the bits indicating that the corresponding choice, and a control circuit controls the first and the second round robin circuit.

Abstract translation: 本实施例的一个方面利用了选择电路，其包括用于存储每个对应于选择的m×n位的信息的第一存储电路。 存储电路指示相应的选择是否处于可选状态。 用于在第二存储电路上执行循环处理的第一循环电路选择包含在相应位串中的一个位，并指示选择处于可选状态。 第二循环电路对具有m位宽的位串执行循环处理，以选择指示相应选择的位之一，并且控制电路控制第一和第二循环电路。

公开(公告)号：US20080095153A1

公开(公告)日：2008-04-24

申请号：US11872344

申请日：2007-10-15

Applicant: Hideyo Fukunaga ,  Takeshi Miyaura

Inventor： Hideyo Fukunaga ,  Takeshi Miyaura

IPC: H04L12/56

CPC classification number: H04L43/028 ,  H04L41/0896 ,  H04L43/18 ,  H04L69/16 ,  H04L69/163

Abstract: A connection-basis identification information storing unit receives connection-basis identification information for identifying a packet for which information on the packet is to be collected, and stores received connection-basis identification information. A connection-basis packet information collecting unit acquires the information receives stores if a packet that is identified by the stored connection-basis identification information is received, and stores acquired information in a predetermined storage unit on the basis of the connection identified by a combination of a transmission source address and a transmission destination address included in the packet.

Abstract translation: 基于连接的识别信息存储单元接收用于识别要收集关于分组的信息的分组的连接基准识别信息，并且存储所接收的基于连接的识别信息。 基于连接的分组信息收集单元获取信息，如果接收到由所存储的基于连接的识别信息识别的分组，则接收存储，并且基于由组合识别的连接将所获取的信息存储在预定的存储单元中 发送源地址和发送目的地地址。

公开(公告)号：US20060098648A1

公开(公告)日：2006-05-11

申请号：US11077868

申请日：2005-03-11

Applicant: Hideyo Fukunaga ,  Katsumi Imamura ,  Yasushi Kurokawa ,  Hideyuki Kudou ,  Yoko Watanabe

Inventor： Hideyo Fukunaga ,  Katsumi Imamura ,  Yasushi Kurokawa ,  Hideyuki Kudou ,  Yoko Watanabe

IPC: H04J3/14 ,  H04J1/16 ,  H04L1/00 ,  H04L12/26 ,  H04L12/56 ,  H04L12/28

CPC classification number: H04L47/6215 ,  H04L47/50

Abstract: A packet transmission device improved in packet transmission efficiency. Each packet input processor generates a pointer and identifies a packet type with respect to a received packet, and generates identification data including the pointer and the packet type identification result. A memory access controller detects a header readout amount of the packet based on the packet type identification result, generates first readout data including the header readout amount and a readout pointer indicative of a storage location of the packet in a shared memory, and adaptively reads out header data of the packet from the shared memory in accordance with the first readout data. A protocol processor analyzes the destination of the read header data, and a packet updater updates the old destination address of the packet to a new one to generate a packet with the updated destination address, and outputs the generated packet.

Abstract translation: 分组传输设备提高了分组传输效率。 每个分组输入处理器产生指针并且相对于接收到的分组标识分组类型，并且生成包括指针和分组类型识别结果的标识数据。 存储器访问控制器基于分组类型识别结果来检测分组的报头读出量，产生包括报头读出量的第一读出数据和表示分组在共享存储器中的存储位置的读出指针，并自适应地读出 根据第一读出数据来自共享存储器的分组的报头数据。 协议处理器分析读取标题数据的目的地，并且分组更新器将分组的旧目的地地址更新为新的分组，以生成具有更新的目的地地址的分组，并输出生成的分组。

公开(公告)号：US07885280B2

公开(公告)日：2011-02-08

申请号：US12320488

申请日：2009-01-27

Applicant: Hideyo Fukunaga ,  Takeshi Sumou ,  Tsutomu Noguchi ,  Katsumi Imamura

Inventor： Hideyo Fukunaga ,  Takeshi Sumou ,  Tsutomu Noguchi ,  Katsumi Imamura

IPC: H04L12/28

CPC classification number: H04L47/10 ,  H04L47/22 ,  H04L47/50 ,  H04L47/527 ,  H04L47/60 ,  H04L49/90 ,  H04L49/9036 ,  H04L49/9078

Abstract: A packet relaying apparatus includes queues holding packet information, and queue control units controlling dequeueing. The dequeueing means transmission of packet information from a queue of a previous stage to a queue of a next stage. The packet relaying apparatus further includes a packet information control unit that, on receiving packet information to be dequeued at the time of dequeueing, returns discard information and data volume corresponding to the received packet information, a first bandwidth adjusting unit that, on determining that the received packet has been discarded, discards the packet information, maintains a usable bandwidth, and transfers the discard information and the data volume to the previous stage, and a second bandwidth adjusting unit that, on receiving the discard information and the data volume from the next stage, adds the data volume to the usable bandwidth and transfers the discard information and the data volume to a previous stage.

Abstract translation: 分组中继装置包括保持分组信息的队列，以及控制出队的队列控制单元。 出队意味着将分组信息从先前阶段的队列传输到下一个队列。 分组中继装置还包括：分组信息控制单元，在接收到出队时出队的分组信息时，返回与所接收的分组信息相对应的丢弃信息和数据量;第一带宽调整单元， 接收到的分组被丢弃，丢弃分组信息，保持可用带宽，并将丢弃信息和数据量传送到前一级;以及第二带宽调整单元，在从下一个接收到丢弃信息和数据量时， 将数据量添加到可用带宽，并将丢弃信息和数据量传送到前一级。

公开(公告)号：US07778174B2

公开(公告)日：2010-08-17

申请号：US11448923

申请日：2006-06-07

Applicant: Yoko Ohta ,  Katsumi Imamura ,  Yasushi Kurokawa ,  Hideyo Fukunaga

Inventor： Yoko Ohta ,  Katsumi Imamura ,  Yasushi Kurokawa ,  Hideyo Fukunaga

IPC: H04J1/16

CPC classification number: H04L47/10 ,  H04L47/215 ,  H04L47/22 ,  H04L47/2441

Abstract: A shaper circuit includes a storage part storing a current token, an add token, and a max token, a subtraction part subtracting a packet length of a dequeue target from the current token stored in the storage part and storing the current token in the storage part, an addition part adding the add token stored in the storage part to the current token stored in the storage part at constant periodic intervals and storing the current token in the storage part, a comparison part comparing the result of the addition with the max token stored in the storage part and preventing the addition result from exceeding the max token, and a determining part outputting a dequeue permission request. A number of bits in a decimal part of the current token are set and a number of bits in an integer part of the add token are set.

Abstract translation: 成形器电路包括存储当前令牌，添加令牌和最大令牌的存储部件，从存储在存储部件中的当前令牌中减去出队目标的分组长度的减法部分，并将当前令牌存储在存储部分中 一个附加部分，将存储在存储部分中的添加令牌以恒定的周期性间隔添加到存储部分中存储的当前令牌，并将当前令牌存储在存储部分中;比较部分，将加法结果与存储的最大令牌进行比较 并且防止相加结果超过最大令牌，以及确定部分输出出队许可请求。 设置当前令牌的小数部分中的位数，并设置加法令牌的整数部分中的位数。