公开(公告)号：US07113311B2

公开(公告)日：2006-09-26

申请号：US10022293

申请日：2001-12-13

申请人： Tsutomu Sasaki ,  Wataru Uchida

发明人： Tsutomu Sasaki ,  Wataru Uchida

IPC分类号： H04N1/00

CPC分类号： H04N1/00307 ,  H04N2201/0015 ,  H04N2201/0024

摘要： A facsimile transmission control procedure for a relay use to relay facsimile communication via a public telephone network between mobile communication control units placed at different places from one another in which such facsimile communication is implemented by the use of a radio link wherein non-standard facilities signal NSF and non-standard facilities set-up signal NSS defined by the Recommendation T.30 are used to identify another communicating party; if the other communicating party can apply a transmission control procedure of the invention, communication is conducted in accordance with such independent transmission control procedure, while if it is not, the communication is made based on the standard Recommendation T.30; and in the independent transmission control procedure, a time margin of each preamble, which is to be added to each of all the binary code signals used in the communication on and after an exchange of NSF and NSS between transmission and reception sides was executed, is reduced to a predetermined time.

公开(公告)号：US08876108B2

公开(公告)日：2014-11-04

申请号：US13469534

申请日：2012-05-11

申请人： Wataru Uchida ,  Ryo Iwasawa ,  Yasuhiko Fuse

发明人： Wataru Uchida ,  Ryo Iwasawa ,  Yasuhiko Fuse

IPC分类号： B65H9/04 ,  B65H9/00

CPC分类号： B65H9/06 ,  B65H9/004 ,  B65H2401/15 ,  B65H2404/532 ,  G03G15/6567 ,  G03G2215/00561 ,  G03G2215/00565

摘要： A sheet transport apparatus includes: a transport portion that transports a sheet; a skew correction portion against which a leading edge of the sheet transported by the transport portion abuts for skew correction, the skew correction portion moving to a position where the skew correction portion does not hinder the transport of the sheet after the skew correction; and a plurality of sheet abutting portions that is provided in the skew correction portion and against that the leading edge of the sheet transported by the transport portion abuts, the plurality of sheet abutting portions respectively including a resin member, and an abutting portion which is provided in the resin member and having an abrasion resistance higher than that of the resin member, and against which the leading edge of the transported sheet abuts.

摘要翻译： 片材输送装置包括：输送片材的输送部; 歪斜校正部分，由传送部分传送的片材的前缘抵靠歪斜校正，偏斜校正部分移动到歪斜校正部分不妨碍在歪斜校正之后片材的传送的位置; 以及设置在所述歪斜校正部分中并且由所述传送部分传送的片材的前缘抵接的多个片材抵接部分，所述多个片材邻接部分分别包括树脂构件和设置的邻接部分 在树脂构件中具有比树脂构件更高的耐磨性，并且运送片的前缘邻接于该树脂构件。

公开(公告)号：US08122416B2

公开(公告)日：2012-02-21

申请号：US12401408

申请日：2009-03-10

申请人： Ken Saito ,  Wataru Uchida

发明人： Ken Saito ,  Wataru Uchida

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5072

摘要： An arrangement verification apparatus that makes it possible to shorten a time it takes to complete a failure/no-failure test on the arrangement of control circuits that control block circuits is provided. The arrangement verification apparatus arranges block circuits to be controlled comprising a semiconductor device and control circuits that control the block circuits over a predetermined floor and conducts a failure/no-failure test on the arrangement of the control circuits. The arrangement verification apparatus includes: a floor plan generation unit that arranges block circuits over a floor based on circuit specifications; a grouping generation unit that hierarchically groups the block circuits arranged over the floor and control circuits described in the circuit specifications based on a predetermined requirement to generate a group tree; a control circuit arrangement unit that arranges the control circuits over the floor according to a predetermined condition and the group tree generated at the grouping generation unit; and a failure/no-failure test unit that conducts a failure/no-failure test on the arrangement of the control circuits by the control circuit arrangement unit.

摘要翻译： 一种布置验证装置，其能够缩短完成对控制块电路的控制电路的布置的故障/无故障测试所花费的时间。 布置验证装置布置要控制的块电路，包括半导体器件和控制电路，控制电路在预定的地板上，并对控制电路的布置进行故障/无故障测试。 布置验证装置包括：平面图生成单元，其基于电路规格在地板上布置块电路; 分组生成单元，其基于预定的要求分层地分组布置在楼层上的块电路和电路规范中描述的控制电路以生成组树; 控制电路布置单元，其根据预定条件和在分组生成单元处生成的组树将控制电路布置在地板上; 以及通过控制电路布置单元对控制电路的布置进行故障/无故障测试的故障/无故障测试单元。

公开(公告)号：US06327610B2

公开(公告)日：2001-12-04

申请号：US09103539

申请日：1998-06-24

申请人： Wataru Uchida ,  Tsutomu Nozaki

发明人： Wataru Uchida ,  Tsutomu Nozaki

IPC分类号： G06F1516

CPC分类号： H04L51/24 ,  H04L12/18 ,  H04L12/1859

摘要： A broadcast communication system in which a terminal unit for sending electronic mail transmits electronic mail data containing text of electronic mail, transmission destination data, a first command indicative of a transmission condition and a second command indicating that broadcast distribution is to be conducted, a mail server, upon reception of electronic mail data containing a second command, transmits a title and an access code of electronic mail text to all of terminal units of transmission destinations indicated by transmission destination data and upon reception of electronic mail data not containing a second command, sends back electronic mail text corresponding to the access code, and a terminal unit for receiving electronic mail, at the time of reception of distribution of electronic mail text, transmits electronic mail data containing an access code to the mail server.

摘要翻译： 一种广播通信系统，其中用于发送电子邮件的终端单元发送包含电子邮件的文本的电子邮件数据，发送目的地数据，表示发送条件的第一命令和指示要进行广播分发的第二命令，邮件 服务器在接收到包含第二命令的电子邮件数据时，向发送目的地数据指示的发送目的地的所有终端单元发送电子邮件文本的标题和访问码，并且在接收到不包含第二命令的电子邮件数据时， 发送对应于访问代码的电子邮件文本，以及用于接收电子邮件的终端单元，在接收到电子邮件文本的分发时，向邮件服务器发送包含访问代码的电子邮件数据。

公开(公告)号：US5678183A

公开(公告)日：1997-10-14

申请号：US642880

申请日：1996-05-06

申请人： Wataru Uchida ,  Shigeru Kimura

发明人： Wataru Uchida ,  Shigeru Kimura

IPC分类号： H04B7/26 ,  H04B7/04 ,  H04B7/06 ,  H04B7/08 ,  H04L27/00 ,  H04W88/06 ,  H04M11/00 ,  H04Q7/32

CPC分类号： H04W88/06 ,  H04B7/04 ,  H04B7/0602 ,  H04B7/0802

摘要： A transmitting apparatus transmits at least one of a main and a supplementary modulated signal in response to a transmitting signal. The apparatus includes a first modulating circuit for modulating the transmitting signal in a main modulation system to produce the main modulated signal. The apparatus also includes a second modulating circuit for modulating the transmitting signal in a supplementary modulation system to produce the supplementary modulated signal. The apparatus further includes a selective supplying circuit for selectively supplying the transmitting signal to at least one of the first and second modulating systems. The apparatus also includes a control circuit connected to the first and second modulating circuits for controlling operation of the first and second modulating circuits and the selective supplying circuit.

摘要翻译： 发送装置响应于发送信号发送主调制信号和辅助调制信号中的至少一个。 该装置包括用于调制主调制系统中的发送信号以产生主调制信号的第一调制电路。 该装置还包括第二调制电路，用于在补充调制系统中调制发送信号以产生补充调制信号。 该装置还包括选择性供应电路，用于选择性地将发送信号提供给第一和第二调制系统中的至少一个。 该装置还包括连接到第一和第二调制电路的控制电路，用于控制第一和第二调制电路和选择性供电电路的操作。

公开(公告)号：US5394404A

公开(公告)日：1995-02-28

申请号：US968884

申请日：1992-10-30

申请人： Wataru Uchida

发明人： Wataru Uchida

IPC分类号： G01R31/317 ,  G01R31/28 ,  G01R31/3185 ,  H03K3/037 ,  H03K3/289 ,  G01K31/29

CPC分类号： G01R31/318541 ,  G01R31/318525

摘要： A flip-flop circuit further includes a diagnosis clock input terminal, a set/reset system control signal input terminal, a first phase shift operation clock input terminal and a second phase shift operation clock input terminal. The flip-flop circuit can be set to a normal operation state, a diagnostic operation state, or a shift operation state by fixing potentials of these input terminals.

摘要翻译： 触发器电路还包括诊断时钟输入端子，置位/复位系统控制信号输入端子，第一相移操作时钟输入端子和第二相移操作时钟输入端子。 触发器电路可以通过固定这些输入端子的电位而被设置为正常操作状态，诊断操作状态或移位操作状态。

公开(公告)号：US20110170905A1

公开(公告)日：2011-07-14

申请号：US13005437

申请日：2011-01-12

申请人： Norio Furuya ,  Wataru Uchida ,  Takeshi Niimura ,  Yusuke Niikawa

发明人： Norio Furuya ,  Wataru Uchida ,  Takeshi Niimura ,  Yusuke Niikawa

IPC分类号： G03G21/18

CPC分类号： G03G21/1853 ,  G03G21/1623 ,  G03G21/1642

摘要： An inexpensive and stable regulating member which can control, without depending on an open/close cover, movement of a cartridge used for an image forming apparatus transportable in a cartridge-mounted state is provided. The regulating member includes a first contact portion which receives a first force applied from the cartridge to inside of the regulating member and a second contact portion which receives a second force that prevents the regulating member from moving from a regulating position by receiving the first force at a position away from a mounting and dismounting path of the cartridge where the cartridge passes when the cartridge is mounted on or dismounted from the apparatus main body.

摘要翻译： 提供一种便宜且稳定的调节构件，其可以不依赖于打开/关闭盖来控制用于可在盒安装状态下运输的图像形成装置的盒的移动。 调节构件包括：第一接触部分，其接收从该盒施加到调节构件内部的第一力;以及第二接触部分，其接收第二力，该第二接触部分接收第二力，其阻止调节构件通过接收第一力而从调节位置移动 远离盒的安装和拆卸路径的位置，当盒被安装在装置主体上或从装置主体上卸下时，该盒通过。

公开(公告)号：US07912888B2

公开(公告)日：2011-03-22

申请号：US11724207

申请日：2007-03-15

申请人： Wataru Uchida

发明人： Wataru Uchida

IPC分类号： G06F7/38

CPC分类号： G06F7/49947 ,  G06F7/52

摘要： A computing device has a rounding processor that inputs therein a set of plural (K) input data IN1 through INK comprising z bits. The rounding processor selects an ensured bit field depending upon the state of usage of each of specific areas A of upper z/2 bits of the 32-bit input data IN1 through INK and rounds the corresponding input data to z/2. As a result of rounding processing, shift information SHIFT of lower (16−n) bits of each discarded non-specific area B is stored in a memory area. D10-1 through D10-K of the rounded respective 16 bits are subjected to multiplication by a multiplier. A digit adjuster shifts multiplication results to the left on the basis of the shift information SHIFT respectively stored in the memory areas to adjust digits.

摘要翻译： 计算设备具有舍入处理器，其中输入一组包含z位的多个（K）输入数据IN1至INK。 舍入处理器根据32位输入数据IN1至INK的高z / 2位的特定区域A的每个使用状态来选择确保的位字段，并将相应的输入数据舍入到z / 2。 作为舍入处理的结果，将每个丢弃的非特定区域B的较低（16-n）比特的移位信息SHIFT存储在存储区域中。 舍入的16位的D10-1至D10-K乘以乘法器。 数字调节器基于分别存储在存储区域中的移位信息SHIFT将相乘结果向左移动以调整数字。

公开(公告)号：US07871076B2

公开(公告)日：2011-01-18

申请号：US11873023

申请日：2007-10-16

申请人： Atsuyuki Yuzawa ,  Wataru Uchida ,  Takeshi Horioka

发明人： Atsuyuki Yuzawa ,  Wataru Uchida ,  Takeshi Horioka

IPC分类号： B65H39/10

CPC分类号： B65H29/58 ,  B65H2301/33312 ,  B65H2402/45 ,  B65H2404/632 ,  B65H2601/11 ,  B65H2801/06

摘要： A sheet conveying apparatus having an excellent performance in jam recovery, and an image forming apparatus provided therewith is provided. The sheet conveying apparatus which may switch the conveying direction of a sheet has: a discharge switching member 60; and a moving unit including a rod 64 and a solenoid 63, which engage with the discharge switching member 60 and moves the discharge switching member 60, in order to switch the conveying direction of a sheet. The discharge switching member 60 and the moving unit may disengage from each other.

摘要翻译： 提供了一种具有优异的卡纸恢复性能的片材输送装置以及与其一起提供的图像形成装置。 可以切换片材的输送方向的片材输送装置具有：排出切换部件60; 以及包括杆64和螺线管63的移动单元，其与排出切换构件60接合并移动排出切换构件60，以便切换片材的输送方向。 放电切换构件60和移动单元可以彼此脱离。

公开(公告)号：US20090158087A1

公开(公告)日：2009-06-18

申请号：US12332915

申请日：2008-12-11

申请人： Hideshi Maeno ,  Wataru Uchida ,  Michinobu Nakao ,  Tatsuya Saito ,  Mitsuo Serizawa

发明人： Hideshi Maeno ,  Wataru Uchida ,  Michinobu Nakao ,  Tatsuya Saito ,  Mitsuo Serizawa

IPC分类号： G11C29/08 ,  G06F11/14 ,  G06F11/26

CPC分类号： G11C29/44 ,  G11C29/4401 ,  G11C29/802

摘要： A semiconductor integrated circuit which can perform repair of at least one memory circuit in RAM, etc. and can promote improvement in the degree of integration is provided. The encoding circuit 3 receives the failure bit data fail [0]-fail [7], encodes these eight-bit failure bit data fail [7:0], and outputs four-bit (the number of compressed bits) encoded data ef [3:0] sequentially. This encoded data ef [3:0] can indicate various kinds of failure information about RAM1. The capture circuit 4 latches the encoded data ef [3:0] which satisfies a predetermined latch condition, as latch data cf [3:0]. The capture circuit 4 can perform a serial shift operation of the latch data cf [3:0], and can output serially the latch data cf [3:0] as the serial data output So.

摘要翻译： 提供了可以对RAM等中的至少一个存储电路进行修复的半导体集成电路，并且可以促进集成度的提高。 编码电路3接收故障位数据失败[0] -fail [7]，对这8位故障位数据失败[7：0]进行编码，并输出4位（压缩位数）编码数据ef [ 3：0]。 该编码数据ef [3：0]可以指示关于RAM1的各种故障信息。 捕获电路4锁存满足预定锁存条件的编码数据ef [3：0]作为锁存数据cf [3：0]。 捕获电路4可以执行锁存数据cf [3：0]的串行移位操作，并且可以串行输出作为串行数据输出So的锁存数据cf [3：0]。