公开(公告)号：US06600190B2

公开(公告)日：2003-07-29

申请号：US09730865

申请日：2000-12-05

申请人： Tyler A. Lowrey ,  Luan C. Tran ,  Alan R. Reinberg ,  D. Mark Durcan

发明人： Tyler A. Lowrey ,  Luan C. Tran ,  Alan R. Reinberg ,  D. Mark Durcan

IPC分类号： H01L27108

CPC分类号： H01L28/90 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/84 ,  H01L28/91

摘要： Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material.

摘要翻译： 描述形成电容器的方法，形成电容器 - 位线存储器电路的方法以及相关的集成电路结构。 在一个实施例中，形成在最上表面上具有最上表面和上覆绝缘材料的电容器存储节点。 随后，电容器电介质功能区域从可覆盖的电容器存储节点的至少一部分可操作地从上覆的绝缘材料离散形成。 在电容器电介质功能区域和上覆绝缘材料上形成电池电极层。

公开(公告)号：US06312988B1

公开(公告)日：2001-11-06

申请号：US09389532

申请日：1999-09-02

申请人： Tyler A. Lowrey ,  Luan C. Tran ,  Alan R. Reinberg ,  D. Mark Durcan

发明人： Tyler A. Lowrey ,  Luan C. Tran ,  Alan R. Reinberg ,  D. Mark Durcan

IPC分类号： H01L218242

CPC分类号： H01L28/90 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/84 ,  H01L28/91

摘要： Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material. In another embodiment, a capacitor storage node is formed having an uppermost surface and a side surface joined therewith. A protective cap is formed over the uppe-most surface and a capacitor dielectric layer is formed over the side surface and protective cap. A cell electrode layer is formed over the side surface of the capacitor storage node. In yet another embodiment, a plurality of capacitor storage nodes are formed arranged in columns. A common cell electrode layer is formed over the plurality of capacitor storage nodes. Cell electrode layer material is removed from between the columns and isolates individual cell electrodes over individual respective capacitor storage nodes. After the removing of the cell electrode layer material, conductive material is formed over portions of remaining cell electrode material thereby placing some of the individual cell electrodes into electrical communication with one another.

摘要翻译： 描述形成电容器的方法，形成电容器 - 位线存储器电路的方法以及相关的集成电路结构。 在一个实施例中，形成在最上表面上具有最上表面和上覆绝缘材料的电容器存储节点。 随后，电容器电介质功能区域从可覆盖的电容器存储节点的至少一部分可操作地从上覆的绝缘材料离散形成。 在电容器电介质功能区域和上覆绝缘材料上形成电池电极层。 在另一个实施例中，电容器存储节点形成为具有与其接合的最上表面和侧表面。 在最大表面上形成保护帽，并且在侧表面和保护盖上形成电容器电介质层。 在电容器存储节点的侧表面上形成电池电极层。 在另一个实施例中，形成多列电容器存储节点。 在多个电容器存储节点上形成公共电极电极层。 从柱之间移除电极电极层材料，并在各个电容器存储节点上隔离各个电池电极。 在除去电池电极层材料之后，在剩余的电池电极材料的部分上形成导电材料，从而使一些单个电池电极彼此电连通。

公开(公告)号：US06995059B2

公开(公告)日：2006-02-07

申请号：US10627468

申请日：2003-07-25

申请人： Tyler A. Lowrey ,  Luan C. Tran ,  Alan R. Reinberg ,  Mark Durcan

发明人： Tyler A. Lowrey ,  Luan C. Tran ,  Alan R. Reinberg ,  Mark Durcan

IPC分类号： H01L21/8242

CPC分类号： H01L28/90 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/84 ,  H01L28/91

摘要： Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material.

公开(公告)号：US06599800B2

公开(公告)日：2003-07-29

申请号：US09954340

申请日：2001-09-14

申请人： Tyler A. Lowrey ,  Luan C. Tran ,  Alan R. Reinberg ,  Mark Durcan

发明人： Tyler A. Lowrey ,  Luan C. Tran ,  Alan R. Reinberg ,  Mark Durcan

IPC分类号： A01L218242

CPC分类号： H01L28/90 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/84 ,  H01L28/91

摘要： Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material.

摘要翻译： 描述形成电容器的方法，形成电容器 - 位线存储器电路的方法以及相关的集成电路结构。 在一个实施例中，形成在最上表面上具有最上表面和上覆绝缘材料的电容器存储节点。 随后，电容器电介质功能区域从可覆盖的电容器存储节点的至少一部分可操作地从上覆的绝缘材料离散形成。 在电容器电介质功能区域和上覆绝缘材料上形成电池电极层。

公开(公告)号：US06790663B2

公开(公告)日：2004-09-14

申请号：US10098659

申请日：2002-03-12

申请人： Robert Kerr ,  Brian Shirley ,  Luan C. Tran ,  Tyler A. Lowrey

发明人： Robert Kerr ,  Brian Shirley ,  Luan C. Tran ,  Tyler A. Lowrey

IPC分类号： H01L214763

CPC分类号： H01L27/10897 ,  H01L21/76895 ,  H01L23/535 ,  H01L27/10891 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and related integrated circuitry constructions are described. In one embodiment, a plurality of conductive lines are formed over a substrate and diffusion regions are formed within the substrate elevationally below the lines. The individual diffusion regions are disposed proximate individual conductive line portions and collectively define therewith individual contact pads with which electrical connection is desired. Insulative material is formed over the conductive line portions and diffusion regions, with contact openings being formed therethrough to expose portions of the individual contact pads. Conductive contacts are formed within the contact openings and in electrical connection with the individual contact pads. In a preferred embodiment, the substrate and diffusion regions provide a pn junction which is configured for biasing into a reverse-biased diode configuration. In operation, the pn junction is sufficiently biased to preclude electrical shorting between the conductive line and the substrate for selected magnitudes of electrical current provided through the conductive line and the conductive material forming the conductive contacts.

摘要翻译： 描述形成触点的方法，接触线的方法，操作集成电路的方法以及相关的集成电路结构。 在一个实施例中，多个导电线形成在衬底之上，扩散区形成在衬底正下方的线下方。 单独的扩散区域设置在各个导电线部分附近，并且与其共同地限定需要电连接的各个接触焊盘。 绝缘材料形成在导电线部分和扩散区域上，其中接触开口穿过其形成以暴露各个接触焊盘的部分。 导电触点形成在接触开口内并与各个接触垫电连接。 在优选实施例中，衬底和扩散区域提供pn结，其被配置为偏置成反向偏置二极管配置。 在操作中，pn结被充分地偏置，以防止导电线和衬底之间的电短路，用于通过导电线和形成导电触点的导电材料提供的选定大小的电流。

公开(公告)号：US06753243B2

公开(公告)日：2004-06-22

申请号：US10280452

申请日：2002-10-25

申请人： Pai-Hung Pan ,  Luan C. Tran ,  Tyler A. Lowrey

发明人： Pai-Hung Pan ,  Luan C. Tran ,  Tyler A. Lowrey

IPC分类号： H01L2144

CPC分类号： H01L27/10888 ,  H01L21/32051 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885

摘要： Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.

摘要翻译： 描述形成接触开口，存储器电路和动态随机存取存储器（DRAM）电路的方法。 在一个实施方案中，字线阵列和位线形成在衬底表面上并由中间绝缘层隔开。 位线的导电部分向外露出，并且在衬底和位线的暴露的导电部分上形成一层材料。 材料层的选定部分与中间层的部分一起被去除，足以使（a）暴露衬底表面的选定区域，并且（b）重新暴露位线的导电部分。 随后形成导电材料以将暴露的衬底区域与各个位线的相关联的导电部分电连接。

公开(公告)号：US06423620B1

公开(公告)日：2002-07-23

申请号：US09935474

申请日：2001-08-21

申请人： Pai-Hung Pan ,  Luan C. Tran ,  Tyler A. Lowrey

发明人： Pai-Hung Pan ,  Luan C. Tran ,  Tyler A. Lowrey

IPC分类号： H01L2144

摘要： Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.

公开(公告)号：US06406954B1

公开(公告)日：2002-06-18

申请号：US09388559

申请日：1999-09-02

申请人： Shubneesh Batra ,  Luan C. Tran ,  Tyler A. Lowrey

发明人： Shubneesh Batra ,  Luan C. Tran ,  Tyler A. Lowrey

IPC分类号： H01L218238

CPC分类号： H01L21/823807 ,  H01L21/823814

摘要： In one aspect, the invention includes a semiconductor processing method of diffusing dopant into both n-type and p-type doped regions of a semiconductive substrate. A semiconductive material is provided. The semiconductive material has a first portion and a second portion. The first portion is a p-type doped portion and the second portion is an n-type doped portion. A mask material is formed over the p-type and n-type doped portions. A first opening is formed to extend through the mask material and to the n-type doped portion. A second opening is formed to extend through the mask material and to the p-type doped portion. Conductively doped polysilicon is formed within the first and second openings. Dopant is out-diffused from the conductively-doped polysilicon and into the n-type and p-type doped portions. In another aspect, the invention includes methods of forming CMOS constructions. In yet another aspect, the invention encompasses methods of forming DRAM constructions.

摘要翻译： 一方面，本发明包括将掺杂剂扩散到半导体衬底的n型和p型掺杂区域中的半导体处理方法。 提供半导体材料。 半导体材料具有第一部分和第二部分。 第一部分是p型掺杂部分，第二部分是n型掺杂部分。 在p型和n型掺杂部分上形成掩模材料。 形成第一开口以延伸穿过掩模材料和n型掺杂部分。 形成第二开口以延伸穿过掩模材料和p型掺杂部分。 导电掺杂多晶硅形成在第一和第二开口内。 掺杂剂从导电掺杂多晶硅扩散到n型和p型掺杂部分。 另一方面，本发明包括形成CMOS结构的方法。 在另一方面，本发明包括形成DRAM结构的方法。

公开(公告)号：US06764934B2

公开(公告)日：2004-07-20

申请号：US10137100

申请日：2002-05-01

申请人： Pai-Hung Pan ,  Luan C. Tran ,  Tyler A. Lowrey

发明人： Pai-Hung Pan ,  Luan C. Tran ,  Tyler A. Lowrey

IPC分类号： H04L2144

CPC分类号： H01L27/10888 ,  H01L21/32051 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885

摘要： Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.

摘要翻译： 描述形成接触开口，存储器电路和动态随机存取存储器（DRAM）电路的方法。 在一个实施方案中，字线阵列和位线形成在衬底表面上并由中间绝缘层隔开。 位线的导电部分向外露出，并且在衬底和位线的暴露的导电部分上形成一层材料。 材料层的选定部分与中间层的部分一起被去除，足以使（a）暴露衬底表面的选定区域，并且（b）重新暴露位线的导电部分。 随后形成导电材料以将暴露的衬底区域与各个位线的相关联的导电部分电连接。

公开(公告)号：US06489226B2

公开(公告)日：2002-12-03

申请号：US09995373

申请日：2001-11-26

申请人： Pai-Hung Pan ,  Luan C. Tran ,  Tyler A. Lowrey

发明人： Pai-Hung Pan ,  Luan C. Tran ,  Tyler A. Lowrey

IPC分类号： H01L2144

CPC分类号： H01L27/10888 ,  H01L21/32051 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885

摘要： Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.

摘要翻译： 描述形成接触开口，存储器电路和动态随机存取存储器（DRAM）电路的方法。 在一个实施方案中，字线阵列和位线形成在衬底表面上并由中间绝缘层隔开。 位线的导电部分向外露出，并且在衬底和位线的暴露的导电部分上形成一层材料。 材料层的选定部分与中间层的部分一起被去除，足以使（a）暴露衬底表面的选定区域，并且（b）重新暴露位线的导电部分。 随后形成导电材料以将暴露的衬底区域与各个位线的相关联的导电部分电连接。