公开(公告)号：US08207576B2

公开(公告)日：2012-06-26

申请号：US11669840

申请日：2007-01-31

申请人： Luan Tran ,  William T Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer K Abatchev ,  Gurtej S Sandhu ,  D. Mark Durcan

发明人： Luan Tran ,  William T Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer K Abatchev ,  Gurtej S Sandhu ,  D. Mark Durcan

IPC分类号： H01L29/66 ,  H01L21/00 ,  G03F7/00

CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088

摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

公开(公告)号：US20100210111A1

公开(公告)日：2010-08-19

申请号：US12769071

申请日：2010-04-28

申请人： Luan Tran ,  William T. Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi (Jenny) Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer K. Abatchev ,  Gurtej S. Sandhu ,  D. Mark Durcan

发明人： Luan Tran ,  William T. Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi (Jenny) Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer K. Abatchev ,  Gurtej S. Sandhu ,  D. Mark Durcan

IPC分类号： H01L21/308

CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088

摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern. Pitch multiplication is accomplished by patterning an amorphous carbon layer. Sidewall spacers are then formed on the amorphous carbon sidewalls which are then removed; the sidewall spacers defining the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is transferred to the BARC. The combined pattern is transferred to an underlying amorphous silicon layer. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, is then etched into the underlying substrate.

摘要翻译： 通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。 间距乘法用于形成第一模式的相对较小的特征。 通过图案化无定形碳层来实现间距倍增。 然后在非晶碳侧壁上形成侧壁间隔物，然后将其去除; 侧壁间隔物限定第一掩模图案。 然后沉积底部抗反射涂层（BARC）以形成平坦表面，并且在BARC上形成光致抗蚀剂层。 接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，其转移到BARC。 将组合图案转移到下面的非晶硅层。 然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。 然后将组合的掩模图案蚀刻到下面的基底中。

公开(公告)号：US07718540B2

公开(公告)日：2010-05-18

申请号：US11670296

申请日：2007-02-01

申请人： Luan Tran ,  William T Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer K Abatchev ,  Gurtej S Sandhu ,  D. Mark Durcan

发明人： Luan Tran ,  William T Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer K Abatchev ,  Gurtej S Sandhu ,  D. Mark Durcan

IPC分类号： H01L21/302

CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088

摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

摘要翻译： 通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。 间距乘法用于形成第一图案的相对较小的特征以及用于形成第二图案的较大特征的常规光刻。 间距倍增通过对光致抗蚀剂进行图案化，然后将该图案蚀刻成无定形碳层来实现。 然后在无定形碳的侧壁上形成侧壁间隔物。 去除无定形碳，留下限定第一掩模图案的侧壁间隔物。 然后将底部抗反射涂层（BARC）沉积在间隔物周围以形成平坦表面，并且在BARC上形成光致抗蚀剂层。 接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，然后将其转印到BARC。 通过第一图案和第二图案形成的组合图案被转印到下面的非晶硅层，并且图案经受碳带以去除BARC和光致抗蚀剂材料。 然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。 具有不同尺寸特征的组合掩模图案然后通过无定形碳硬掩模层蚀刻到下面的衬底中。

公开(公告)号：US20100092891A1

公开(公告)日：2010-04-15

申请号：US12636581

申请日：2009-12-11

申请人： Luan Tran ,  William T. Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer K. Abatchev ,  Gurtej S. Sandhu ,  D. Mark Durcan

发明人： Luan Tran ,  William T. Rericha ,  John Lee ,  Ramakanth Alapati ,  Sheron Honarkhah ,  Shuang Meng ,  Puneet Sharma ,  Jingyi Bai ,  Zhiping Yin ,  Paul Morgan ,  Mirzafer K. Abatchev ,  Gurtej S. Sandhu ,  D. Mark Durcan

IPC分类号： G03F7/20

CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3088

摘要： Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

摘要翻译： 通过使用通过组合两个单独形成的图案形成的掩模蚀刻衬底来形成集成电路的不同尺寸的特征。 间距乘法用于形成第一图案的相对较小的特征以及用于形成第二图案的较大特征的常规光刻。 间距倍增通过对光致抗蚀剂进行图案化，然后将该图案蚀刻成无定形碳层来实现。 然后在无定形碳的侧壁上形成侧壁间隔物。 去除无定形碳，留下限定第一掩模图案的侧壁间隔物。 然后将底部抗反射涂层（BARC）沉积在间隔物周围以形成平坦表面，并且在BARC上形成光致抗蚀剂层。 接下来通过常规光刻法将光致抗蚀剂图案化以形成第二图案，然后将其转印到BARC。 通过第一图案和第二图案形成的组合图案被转印到下面的非晶硅层，并且图案经受碳带以去除BARC和光致抗蚀剂材料。 然后将组合图案转移到氧化硅层，然后转移到无定形碳掩模层。 具有不同尺寸特征的组合掩模图案然后通过无定形碳硬掩模层蚀刻到下面的衬底中。

公开(公告)号：US07629693B2

公开(公告)日：2009-12-08

申请号：US11492513

申请日：2006-07-24

申请人： Mirzafer K. Abatchev ,  Gurtej Sandhu ,  Luan Tran ,  William T. Rericha ,  D. Mark Durcan

发明人： Mirzafer K. Abatchev ,  Gurtej Sandhu ,  Luan Tran ,  William T. Rericha ,  D. Mark Durcan

IPC分类号： H01L29/40 ,  H01L23/52

CPC分类号： H01L21/0337 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  Y10S438/947 ,  Y10S438/95

摘要： Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.

摘要翻译： 集成电路的阵列和周边中的不同尺寸的特征在单个步骤中在衬底上图案化。 特别地，组合两个单独形成的图案的混合图案形成在单个掩模层上，然后转移到下面的基底。 单独形成的图案中的第一个通过间距倍增形成，并且通过常规光刻形成第二个单独形成的图案。 单独形成的图案中的第一个包括低于用于形成第二个单独形成的图案的光刻工艺的分辨率的线。 这些线通过在光致抗蚀剂上形成图案然后将该图案刻蚀成无定形碳层而制成。 在无定形碳的侧壁上形成宽度小于无定形碳的未蚀刻部分的宽度的侧壁盘。 然后去除无定形碳，留下侧壁间隔物作为掩模图案。 因此，间隔物形成具有小于用于在光致抗蚀剂上形成图案的光刻工艺的分辨率的特征尺寸的掩模。 保护材料沉积在间隔物周围。 使用硬掩模进一步保护间隔物，然后在硬掩模上形成并图案化光致抗蚀剂。 光致抗蚀剂图案通过硬掩模转印到保护材料上。 然后将由间隔物和临时材料制成的图案转移到下面的无定形碳硬掩模层。 具有不同尺寸特征的图案然后被转移到下面的基底。

公开(公告)号：US07625795B2

公开(公告)日：2009-12-01

申请号：US11217742

申请日：2005-09-01

申请人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez ,  Er-Xuan Ping

发明人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez ,  Er-Xuan Ping

IPC分类号： H01L21/8242

CPC分类号： H01L28/91 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/65 ,  Y10S257/905

摘要： Container capacitor structure and method of construction. An etch mask and etch are used to expose portions of an exterior surface of an electrode (“bottom electrodes”) of the structure. The etch provides a recess between proximal pairs of container capacitor structures, which is available for forming additional capacitance. A capacitor dielectric and top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Surface area common to both the first electrode and second electrodes is increased over using only the interior surface, providing additional capacitance without decreasing spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

摘要翻译： 集装箱电容器结构及其施工方法。 蚀刻掩模和蚀刻用于暴露结构的电极（“底部电极”）的外表面的部分。 蚀刻在容器电容器结构的近端对之间提供凹槽，其可用于形成额外的电容。 电容器电介质和顶电极分别形成在第一电极的内表面和外表面的两个部分上并与其相邻。 第一电极和第二电极两者共同的表面积仅通过使用内表面增加，提供额外的电容而不减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。 电容器电介质和第二电极部分的清除可以在衬底组件的上部位置进行，与在接触通孔的底部位置处的清除相反。

公开(公告)号：US07579235B2

公开(公告)日：2009-08-25

申请号：US11545252

申请日：2006-10-10

申请人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez ,  Er-Xuan Ping

发明人： D. Mark Durcan ,  Trung T. Doan ,  Roger R. Lee ,  Fernando Gonzalez ,  Er-Xuan Ping

IPC分类号： H01L21/8242

CPC分类号： H01L28/91 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10888 ,  H01L28/65 ,  Y10S257/905

摘要： Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

公开(公告)号：US20090209080A1

公开(公告)日：2009-08-20

申请号：US12430621

申请日：2009-04-27

申请人： Gurtej S. Sandhu ,  D. Mark Durcan

发明人： Gurtej S. Sandhu ,  D. Mark Durcan

IPC分类号： H01L27/10 ,  H01G4/30

CPC分类号： H01L28/90 ,  H01L27/0805 ,  Y10T29/43

摘要： The invention includes methods of forming pluralities of capacitors. In one implementation, a method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes within a capacitor array area over a substrate. The capacitor electrodes comprise outer lateral sidewalls. The plurality of capacitor electrodes is supported at least in part with a retaining structure which engages the outer lateral sidewalls. The retaining structure is formed at least in part by etching a layer of material which is not masked anywhere within the capacitor array area to form said retaining structure. The plurality of capacitor electrodes is incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.

摘要翻译： 本发明包括形成多个电容器的方法。 在一个实施方式中，形成多个电容器的方法包括在衬底上的电容器阵列区域内设置多个电容器电极。 电容器电极包括外侧壁。 多个电容器电极至少部分地具有与外侧向侧壁接合的保持结构。 保持结构至少部分地通过蚀刻在电容器阵列区域内的任何地方未被掩蔽的材料层以形成所述保持结构而形成。 多个电容器电极被并入多个电容器中。 考虑了其他方面和实现。

公开(公告)号：US07547640B2

公开(公告)日：2009-06-16

申请号：US11492323

申请日：2006-07-24

申请人： Mirzafer K. Abatchev ,  Gurtej Sandhu ,  Luan Tran ,  William T. Rericha ,  D. Mark Durcan

发明人： Mirzafer K. Abatchev ,  Gurtej Sandhu ,  Luan Tran ,  William T. Rericha ,  D. Mark Durcan

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/0337 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  Y10S438/947 ,  Y10S438/95

摘要： Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate.

公开(公告)号：US20070235783A9

公开(公告)日：2007-10-11

申请号：US11185186

申请日：2005-07-19

申请人： Gurtej S. Sandhu ,  D. Mark Durcan

发明人： Gurtej S. Sandhu ,  D. Mark Durcan

IPC分类号： H01L27/108 ,  H01L21/762

CPC分类号： H01L29/0649 ,  G11C14/0018 ,  H01L21/76232 ,  H01L27/10805 ,  H01L27/11521 ,  H01L29/0653

摘要： The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The bottom portions can have substantially vertical sidewalls, and can join to the upper portions at steps which extend substantially perpendicularly from the sidewalls. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

摘要翻译： 本发明包括具有沟槽隔离区域的半导体结构。 沟槽隔离区域的沟槽可以包括底部的窄底部部分和上部宽部分。 电绝缘材料可以填充上部宽部分，同时留下狭窄底部内的空隙。 底部可以具有基本上垂直的侧壁，并且可以从侧壁大致垂直延伸的台阶连接到上部。 沟槽隔离区域可以并入存储器阵列中，和/或可并入到电子系统中。 本发明还包括形成半导体结构的方法。