公开(公告)号：US11923846B2

公开(公告)日：2024-03-05

申请号：US17673772

申请日：2022-02-16

Applicant: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Kyung Rok Kim ,  Jae Won Jeong ,  Youngeun Choi ,  Wooseok Kim ,  Jae Hyeon Jun

IPC: H03K19/00 ,  H03K19/08 ,  H03K19/20

CPC classification number: H03K19/08 ,  H03K19/20

Abstract: A ternary logic circuit includes: a first inverter unit; a second inverter unit arranged in parallel with the first inverter unit; a first junction unit arranged between the first inverter unit and an output terminal and including a tunnel PN junction; and a second junction unit arranged between the second inverter unit and the output terminal and including a tunnel PN junction, wherein, when an absolute value of an input voltage applied to an input terminal is less than a first input voltage, the output terminal outputs a first output voltage, and when the absolute value of the input voltage is greater than the first input voltage and less than a second input voltage, the output terminal outputs a second output voltage, and when the absolute value of the input terminal is greater than the second input voltage, the output terminal outputs a third output voltage.

公开(公告)号：US20220407520A1

公开(公告)日：2022-12-22

申请号：US17673772

申请日：2022-02-16

Applicant: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Kyung Rok Kim ,  Jae Won Jeong ,  Youngeun Choi ,  Wooseok Kim ,  Jae Hyeon Jun

IPC: H03K19/08

Abstract: A ternary logic circuit includes: a first inverter unit; a second inverter unit arranged in parallel with the first inverter unit; a first junction unit arranged between the first inverter unit and an output terminal and including a tunnel PN junction; and a second junction unit arranged between the second inverter unit and the output terminal and including a tunnel PN junction, wherein, when an absolute value of an input voltage applied to an input terminal is less than a first input voltage, the output terminal outputs a first output voltage, and when the absolute value of the input voltage is greater than the first input voltage and less than a second input voltage, the output terminal outputs a second output voltage, and when the absolute value of the input terminal is greater than the second input voltage, the output terminal outputs a third output voltage.