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    TUNNEL FIELD EFFECT TRANSISTOR AND TERNARY INVERTER INCLUDING THE SAME
    4.
    发明申请
    TUNNEL FIELD EFFECT TRANSISTOR AND TERNARY INVERTER INCLUDING THE SAME 有权

    公开(公告)号：US20230006054A1

    公开(公告)日：2023-01-05

    申请号：US17673766

    申请日：2022-02-16

    Applicant: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

    Inventor： Kyung Rok Kim ,  Ji Won Chang ,  Jae Won Jeong ,  Youngeun Choi ,  Wooseok Kim

    IPC: H01L29/66 ,  H01L27/092 ,  H01L29/786

    Abstract: A tunnel field effect transistor includes a source region and a drain region, positioned on a substrate, a channel region positioned between the source region and the drain region and having a first length in a first direction, a gate electrode positioned on the channel region, and a gate insulating layer positioned between the channel region and the gate electrode, wherein the source region is doped with impurities of a first conductivity type and the drain region is doped with impurities of a second conductivity type that is different from the first conductivity type, and one of the source region and the drain region includes an extension region extending toward the other region, the extension region being positioned under the channel region to form a constant current independent of a gate voltage of the gate electrode.

    Ternary logic circuit
    5.
    发明授权
    Ternary logic circuit 有权

    公开(公告)号：US11923846B2

    公开(公告)日：2024-03-05

    申请号：US17673772

    申请日：2022-02-16

    Applicant: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

    Inventor： Kyung Rok Kim ,  Jae Won Jeong ,  Youngeun Choi ,  Wooseok Kim ,  Jae Hyeon Jun

    IPC: H03K19/00 ,  H03K19/08 ,  H03K19/20

    CPC classification number: H03K19/08 ,  H03K19/20

    Abstract: A ternary logic circuit includes: a first inverter unit; a second inverter unit arranged in parallel with the first inverter unit; a first junction unit arranged between the first inverter unit and an output terminal and including a tunnel PN junction; and a second junction unit arranged between the second inverter unit and the output terminal and including a tunnel PN junction, wherein, when an absolute value of an input voltage applied to an input terminal is less than a first input voltage, the output terminal outputs a first output voltage, and when the absolute value of the input voltage is greater than the first input voltage and less than a second input voltage, the output terminal outputs a second output voltage, and when the absolute value of the input terminal is greater than the second input voltage, the output terminal outputs a third output voltage.

    TERNARY INVERTER AND METHOD OF MANUFACTURING THE SAME
    6.
    发明申请
    TERNARY INVERTER AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20230005909A1

    公开(公告)日：2023-01-05

    申请号：US17673754

    申请日：2022-02-16

    Applicant: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

    Inventor： Kyung Rok Kim ,  Jae Won Jeong ,  Youngeun Choi ,  Wooseok Kim

    IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

    Abstract: Provided are an inverter including a first source and drain, an interlayer insulating film on the first source, a second source on the interlayer insulating film, a second drain on the first drain, a first channel between the first source and drain, a second channel over the first channel between the second source and drain, a gate insulating film covering outer surfaces of the first and second channel, a part of a surface of the first source in the direction to the first drain, a part of a surface of the second source in the direction to the second drain, a part of a surface of the first drain in the direction to the first source, and a part of a surface of the second drain in the direction to the second source, and a gate electrode between the first source and drain and between the second source and drain.

    MEMORY DEVICE INCLUDING TERNARY MEMORY CELL
    7.
    发明申请
    MEMORY DEVICE INCLUDING TERNARY MEMORY CELL 有权

    公开(公告)号：US20220413800A1

    公开(公告)日：2022-12-29

    申请号：US17672650

    申请日：2022-02-15

    Applicant: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

    Inventor： Kyung Rok Kim ,  Jae Won Jeong ,  Youngeun Choi ,  Wooseok Kim ,  Myoung Kim

    IPC: G06F7/523 ,  G11C15/04 ,  G06F7/50

    Abstract: Provided is a memory device for a logic-in-memory. The memory cell includes: a ternary memory cell for storing ternary data: and a weight cell for controlling a current flowing in an operation line on the basis of a weight signal transmitted from the ternary memory cell and an activation signal transmitted via an activation line, wherein the weight cell includes a first transistor for receiving an input of weight data from a first node corresponding to a stored value of the ternary memory cell, a second transistor for receiving an input of inversed weight data from a second node corresponding to an inversed stored value of the ternary memory cell, and a third transistor for receiving an input of an activation signal transmitted via the activation line.

    TERNARY CONTENT ADDRESSABLE MEMORY DEVICE BASED ON TERNARY MEMORY CELL
    9.
    发明申请
    TERNARY CONTENT ADDRESSABLE MEMORY DEVICE BASED ON TERNARY MEMORY CELL 有权

    公开(公告)号：US20220415396A1

    公开(公告)日：2022-12-29

    申请号：US17672662

    申请日：2022-02-15

    Applicant: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

    Inventor： Kyung Rok Kim ,  Jae Won Jeong ,  Youngeun Choi ,  Wooseok Kim

    IPC: G11C15/04 ,  G11C11/412 ,  G11C11/419

    Abstract: Disclosed is a TCAM device based on a ternary memory cell. A TCAM cell includes a ternary memory cell for storing ternary data and a comparison circuit for obtaining a stored value stored in the ternary memory cell and a search value input via a search line of a search driver, identifying a data match between the stored value and the search value, and outputting a result of the identification via a match line. The comparison circuit includes a first transistor pair that receives an inverted stored value that is an inverted value of the stored value of the ternary memory cell and the search value and a second transistor pair that receives the stored value of the ternary memory cell and an inverted search value that is an inverted value of the search value. The first transistor pair and the second transistor pair are connected in parallel to each other.

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