公开(公告)号：US11923846B2

公开(公告)日：2024-03-05

申请号：US17673772

申请日：2022-02-16

Applicant: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Kyung Rok Kim ,  Jae Won Jeong ,  Youngeun Choi ,  Wooseok Kim ,  Jae Hyeon Jun

IPC: H03K19/00 ,  H03K19/08 ,  H03K19/20

CPC classification number: H03K19/08 ,  H03K19/20

Abstract: A ternary logic circuit includes: a first inverter unit; a second inverter unit arranged in parallel with the first inverter unit; a first junction unit arranged between the first inverter unit and an output terminal and including a tunnel PN junction; and a second junction unit arranged between the second inverter unit and the output terminal and including a tunnel PN junction, wherein, when an absolute value of an input voltage applied to an input terminal is less than a first input voltage, the output terminal outputs a first output voltage, and when the absolute value of the input voltage is greater than the first input voltage and less than a second input voltage, the output terminal outputs a second output voltage, and when the absolute value of the input terminal is greater than the second input voltage, the output terminal outputs a third output voltage.

公开(公告)号：US20230005909A1

公开(公告)日：2023-01-05

申请号：US17673754

申请日：2022-02-16

Applicant: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Kyung Rok Kim ,  Jae Won Jeong ,  Youngeun Choi ,  Wooseok Kim

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: Provided are an inverter including a first source and drain, an interlayer insulating film on the first source, a second source on the interlayer insulating film, a second drain on the first drain, a first channel between the first source and drain, a second channel over the first channel between the second source and drain, a gate insulating film covering outer surfaces of the first and second channel, a part of a surface of the first source in the direction to the first drain, a part of a surface of the second source in the direction to the second drain, a part of a surface of the first drain in the direction to the first source, and a part of a surface of the second drain in the direction to the second source, and a gate electrode between the first source and drain and between the second source and drain.

公开(公告)号：US20220413800A1

公开(公告)日：2022-12-29

申请号：US17672650

申请日：2022-02-15

Applicant: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Kyung Rok Kim ,  Jae Won Jeong ,  Youngeun Choi ,  Wooseok Kim ,  Myoung Kim

IPC: G06F7/523 ,  G11C15/04 ,  G06F7/50

Abstract: Provided is a memory device for a logic-in-memory. The memory cell includes: a ternary memory cell for storing ternary data: and a weight cell for controlling a current flowing in an operation line on the basis of a weight signal transmitted from the ternary memory cell and an activation signal transmitted via an activation line, wherein the weight cell includes a first transistor for receiving an input of weight data from a first node corresponding to a stored value of the ternary memory cell, a second transistor for receiving an input of inversed weight data from a second node corresponding to an inversed stored value of the ternary memory cell, and a third transistor for receiving an input of an activation signal transmitted via the activation line.

公开(公告)号：US20220084584A1

公开(公告)日：2022-03-17

申请号：US17424490

申请日：2020-04-03

Applicant: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Kyung Rok Kim ,  Jae Won Jeong ,  Young Eun Choi

IPC: G11C11/419 ,  G11C11/412 ,  G11C11/4094 ,  G11C11/408 ,  H03K19/017

Abstract: In a memory device including a ternary memory cell, the ternary memory cell may include: a first inverter and a second inverter cross-coupled in a first node and a second node and including a pull-up device and a pull-down device configured to have a constant current pass therethrough upon turn-off; a first read transistor and a first write transistor which are connected to each other in parallel between the first node and a first bit line; and a second read transistor and a second write transistor which are connected to each other in parallel between the second node and a second bit line, wherein the first read transistor and the second read transistor may have a read access current, which is less than or equal to the constant current, pass therethrough in response to an activated read word line.

公开(公告)号：US20230006054A1

公开(公告)日：2023-01-05

申请号：US17673766

申请日：2022-02-16

Applicant: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Kyung Rok Kim ,  Ji Won Chang ,  Jae Won Jeong ,  Youngeun Choi ,  Wooseok Kim

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/786

Abstract: A tunnel field effect transistor includes a source region and a drain region, positioned on a substrate, a channel region positioned between the source region and the drain region and having a first length in a first direction, a gate electrode positioned on the channel region, and a gate insulating layer positioned between the channel region and the gate electrode, wherein the source region is doped with impurities of a first conductivity type and the drain region is doped with impurities of a second conductivity type that is different from the first conductivity type, and one of the source region and the drain region includes an extension region extending toward the other region, the extension region being positioned under the channel region to form a constant current independent of a gate voltage of the gate electrode.

公开(公告)号：US20250081564A1

公开(公告)日：2025-03-06

申请号：US18952961

申请日：2024-11-19

Applicant: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Kyung Rok Kim ,  Ji Won Chang ,  Jae Won Jeong ,  Youngeun Choi ,  Wooseok Kim

IPC: H01L29/10 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: Provided is a transistor including: a constant current formation layer; a channel layer provided on the constant current formation layer; a pair of source/drain regions spaced apart from each other, with the channel layer therebetween on the constant current formation layer; a gate electrode provided on the channel layer; and a gate ferroelectric film provided between the gate electrode and the channel layer.

公开(公告)号：US20240379786A1

公开(公告)日：2024-11-14

申请号：US18780300

申请日：2024-07-22

Applicant: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Kyung Rok Kim ,  Ji Won Chang ,  Jae Won Jeong ,  Youngeun Choi ,  Wooseok Kim

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H03K19/0948

Abstract: A transistor includes a substrate; a pair of constant current forming regions provided in the substrate; a pair of source/drain regions respectively provided on the pair of constant current forming regions in the substrate; and a gate structure provided between the pair of source/drain regions, wherein any one of the constant current forming regions immediately adjacent to any one of the pair of source/drain regions serving as a drain forms a constant current between the any one of the pair of source/drain region serving as the drain and the any one of the constant current forming regions.

公开(公告)号：US20240162230A1

公开(公告)日：2024-05-16

申请号：US18411943

申请日：2024-01-12

Applicant: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Kyung Rok Kim ,  Jae Won Jeong ,  Young Eun Choi ,  Woo Seok Kim ,  Jiwon Chang

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L29/66492 ,  H01L29/7833

Abstract: A transistor device includes a substrate, a fin structure extending on the substrate in a direction parallel to a top surface of the substrate, a source region and a drain region provided at an upper portion of the fin structure, a constant current generating layer provided at a lower portion of the fin structure, a gate insulating film provided on both side surfaces and a top surface of the upper portion of the fin structure, and a gate electrode provided on the gate insulating film, wherein the gate electrode is provided on the fin structure and between the source region and the drain region, the constant current generating layer generates a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

公开(公告)号：US20220285507A1

公开(公告)日：2022-09-08

申请号：US17636026

申请日：2020-11-19

Applicant: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Kyung Rok Kim ,  Ji Won Chang ,  Jae Won Jeong ,  Youngeun Choi ,  Wooseok Kim

IPC: H01L29/417 ,  H03K19/0948 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238

Abstract: A transistor includes a substrate; a pair of constant current forming regions provided in the substrate; a pair of source/drain regions respectively provided on the pair of constant current forming regions in the substrate; and a gate structure provided between the pair of source/drain regions, wherein any one of the constant current forming regions immediately adjacent to any one of the pair of source/drain regions serving as a drain forms a constant current between the any one of the pair of source/drain region serving as the drain and the any one of the constant current forming regions.

公开(公告)号：US20220085017A1

公开(公告)日：2022-03-17

申请号：US17419692

申请日：2019-12-16

Applicant: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Kyung Rok Kim ,  Jae Won Jeong ,  Young Eun Choi ,  Woo Seok Kim

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66

Abstract: A transistor device includes a substrate, a source region provided on the substrate, a drain region spaced apart from the source region in a direction parallel to a top surface of the substrate, a pair of constant current generating patterns provided in the substrate to be adjacent to the source region and the drain region, respectively, a gate electrode provided on the substrate and between the source region and the drain region, and a gate insulating film interposed between the gate electrode and the substrate, wherein, the pair of constant current generating patterns generate a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.