公开(公告)号：US20190115259A1

公开(公告)日：2019-04-18

申请号：US15803865

申请日：2017-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jiun-Lin Yeh ,  Hsueh-Chih Tseng ,  Chia-Chen Tsai ,  Ta-Kang Lo

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/266

Abstract: A manufacturing method of a semiconductor device includes following steps. First gate structures and second gate structures are formed on a first region and a second region of a semiconductor substrate respectively. A spacing distance between the second gate structures is larger than that between the first gate structures. A first ion implantation is preformed to form a first doped region between the first gate structures. A second ion implantation is performed to form a second doped region between the second gate structures. A tilt angle of the second ion implantation is larger than that of the first ion implantation. An implantation dose of the second ion implantation is lower than that of the first ion implantation. An etching process is performed to at least partially remove the first doped region to form a first recess and at least partially remove the second doped region to form a second recess.

公开(公告)号：US09634002B1

公开(公告)日：2017-04-25

申请号：US15057079

申请日：2016-02-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Tsai ,  Hung-Chang Chang ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Shang-Jr Chen

IPC: H01L27/08 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L21/823468 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device and method of manufacturing the same are provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.

公开(公告)号：US10607891B2

公开(公告)日：2020-03-31

申请号：US15803865

申请日：2017-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jiun-Lin Yeh ,  Hsueh-Chih Tseng ,  Chia-Chen Tsai ,  Ta-Kang Lo

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/265 ,  H01L21/266 ,  H01L27/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/84

Abstract: A manufacturing method of a semiconductor device includes following steps. First gate structures and second gate structures are formed on a first region and a second region of a semiconductor substrate respectively. A spacing distance between the second gate structures is larger than that between the first gate structures. A first ion implantation is preformed to form a first doped region between the first gate structures. A second ion implantation is performed to form a second doped region between the second gate structures. A tilt angle of the second ion implantation is larger than that of the first ion implantation. An implantation dose of the second ion implantation is lower than that of the first ion implantation. An etching process is performed to at least partially remove the first doped region to form a first recess and at least partially remove the second doped region to form a second recess.

公开(公告)号：US09779998B2

公开(公告)日：2017-10-03

申请号：US15450037

申请日：2017-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Tsai ,  Hung-Chang Chang ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Shang-Jr Chen

IPC: H01L21/82 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823468 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device is provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.

公开(公告)号：US20170221766A1

公开(公告)日：2017-08-03

申请号：US15450037

申请日：2017-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Tsai ,  Hung-Chang Chang ,  Ta-Kang Lo ,  Tsai-Fu Chen ,  Shang-Jr Chen

IPC: H01L21/8234 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823468 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device is provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.