公开(公告)号：US20180122705A1

公开(公告)日：2018-05-03

申请号：US15342114

申请日：2016-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tai-You Chen ,  Cheng-Guo Chen ,  Kun-Yuan Wu ,  Chiu-Sheng Ho ,  Po-Kang Yang ,  Ta-Kang Lo ,  Shang-Jr Chen

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L21/823807 ,  H01L21/28088 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785

Abstract: First, a substrate having a first region and a second region is provided, a first gate structure is formed on the first region and a second gate structure is formed on the second region, an interlayer dielectric (ILD) layer is formed around the first gate structure and the second gate structure, and the first gate structure and the second gate structure are removed to expose the substrate on the first region and the second region. Next, part of the substrate on the first region is removed to form a first recess and part of the substrate on the second region is removed to form a second recess, in which the depths of the first recess and the second recess are different. Next, a first metal gate is formed on the first region and a second metal gate is formed on the second region.

公开(公告)号：US09960083B1

公开(公告)日：2018-05-01

申请号：US15342114

申请日：2016-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tai-You Chen ,  Cheng-Guo Chen ,  Kun-Yuan Wu ,  Chiu-Sheng Ho ,  Po-Kang Yang ,  Ta-Kang Lo ,  Shang-Jr Chen

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L21/823807 ,  H01L21/28088 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785

Abstract: First, a substrate having a first region and a second region is provided, a first gate structure is formed on the first region and a second gate structure is formed on the second region, an interlayer dielectric (ILD) layer is formed around the first gate structure and the second gate structure, and the first gate structure and the second gate structure are removed to expose the substrate on the first region and the second region. Next, part of the substrate on the first region is removed to form a first recess and part of the substrate on the second region is removed to form a second recess, in which the depths of the first recess and the second recess are different. Next, a first metal gate is formed on the first region and a second metal gate is formed on the second region.

公开(公告)号：US10276663B2

公开(公告)日：2019-04-30

申请号：US15213370

申请日：2016-07-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Guo Chen ,  Kun-Yuan Wu ,  Tai-You Chen ,  Chiu-Sheng Ho ,  Po-Kang Yang ,  Ta-Kang Lo

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/739 ,  H01L29/267

Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.

公开(公告)号：US20180019341A1

公开(公告)日：2018-01-18

申请号：US15213370

申请日：2016-07-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Guo Chen ,  Kun-Yuan Wu ,  Tai-You Chen ,  Chiu-Sheng Ho ,  Po-Kang Yang ,  Ta-Kang Lo

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66636 ,  H01L29/7391 ,  H01L29/7848 ,  H01L29/785

Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.

公开(公告)号：US10707305B2

公开(公告)日：2020-07-07

申请号：US16354126

申请日：2019-03-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Guo Chen ,  Kun-Yuan Wu ,  Tai-You Chen ,  Chiu-Sheng Ho ,  Po-Kang Yang ,  Ta-Kang Lo

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/739 ,  H01L29/267

Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.

公开(公告)号：US20190214463A1

公开(公告)日：2019-07-11

申请号：US16354126

申请日：2019-03-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Guo Chen ,  Kun-Yuan Wu ,  Tai-You Chen ,  Chiu-Sheng Ho ,  Po-Kang Yang ,  Ta-Kang Lo

IPC: H01L29/08 ,  H01L29/739 ,  H01L29/78 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66636 ,  H01L29/7391 ,  H01L29/7848 ,  H01L29/785

Abstract: A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.