公开(公告)号：US10170369B1

公开(公告)日：2019-01-01

申请号：US15806295

申请日：2017-11-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Lin Hsu ,  En-Chiuan Liou

IPC: H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having a fin structure extending along a first direction. The fin structure protrudes from a top surface of a trench isolation region and has a first height. A plurality of gate lines including a first gate line and a second gate line extend along a second direction and striding across the fin structure. The first gate line has a discontinuity directly above a gate cut region. The second gate line is disposed in proximity to a dummy fin region, and does not overlap with the dummy fin region. The fin structure has a second height within the dummy fin region, and the second height is smaller than the first height.

公开(公告)号：US20200013724A1

公开(公告)日：2020-01-09

申请号：US16049826

申请日：2018-07-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Zheng-Feng Chen ,  Sho-Shen Lee ,  En-Chiuan Liou ,  Hsiao-Lin Hsu ,  Yi-Ting Chen ,  Lu-Wei Kuo

IPC: H01L23/544 ,  H01L27/108 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3213

Abstract: A method of forming an overlay mark structure includes the following steps. An insulation layer is formed on a substrate. A first overlay mark is formed in the insulation layer. A metal layer is formed on the substrate. The metal layer covers the insulation layer and the first overlay mark. The metal layer on the first overlay mark is removed. A top surface of the first overlay mark is lower than a top surface of the insulation layer after the step of removing the metal layer on the first overlay mark. A second overlay mark is formed on the metal layer. In the method of forming the overlay mark structure, the first overlay mark may not be covered by the metal layer for avoiding influences on related measurements, and the second overlay mark may be formed on the metal layer for avoiding related defects generated by the height difference.

公开(公告)号：US10177094B1

公开(公告)日：2019-01-08

申请号：US15954591

申请日：2018-04-16

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Hsiao-Lin Hsu ,  En-Chiuan Liou ,  Yi-Ting Chen ,  Sho-Shen Lee

IPC: H01L23/544 ,  G01B11/27 ,  H01L21/66 ,  H01L21/8234

Abstract: A measurement make includes four rectangular regions having a first region and a second region arranged diagonally, and a third region and a fourth region arranged diagonally. A plurality sets of first inner pattern blocks, first middle pattern blocks, and first outer reference pattern blocks, are disposed within the first region. Each first inner pattern block comprises line patterns and a block pattern. The block pattern has multiple space patterns arranged therein. The first inner pattern block is rotational symmetrical to the first middle pattern block.

公开(公告)号：US10600692B2

公开(公告)日：2020-03-24

申请号：US16200670

申请日：2018-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Lin Hsu ,  En-Chiuan Liou

IPC: H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having a fin structure extending along a first direction. The fin structure protrudes from a top surface of a trench isolation region and has a first height. A plurality of gate lines including a first gate line and a second gate line extend along a second direction and striding across the fin structure. The first gate line has a discontinuity directly above a gate cut region. The second gate line is disposed in proximity to a dummy fin region, and does not overlap with the dummy fin region. The fin structure has a second height within the dummy fin region, and the second height is smaller than the first height.

公开(公告)号：US10373915B1

公开(公告)日：2019-08-06

申请号：US16202104

申请日：2018-11-28

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Hsiao-Lin Hsu ,  En-Chiuan Liou ,  Yi-Ting Chen ,  Sho-Shen Lee

IPC: H01L23/544 ,  H01L21/66 ,  G01B11/27 ,  H01L21/8234

Abstract: A measurement make includes four rectangular regions having a first region and a second region arranged diagonally, and a third region and a fourth region arranged diagonally. A plurality sets of first inner pattern blocks, first middle pattern blocks, and first outer reference pattern blocks, are disposed within the first region. Each first inner pattern block comprises line patterns and a block pattern. The block pattern has multiple space patterns arranged therein. The first inner pattern block is rotational symmetrical to the first middle pattern block.

公开(公告)号：US10529667B1

公开(公告)日：2020-01-07

申请号：US16049826

申请日：2018-07-31

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Zheng-Feng Chen ,  Sho-Shen Lee ,  En-Chiuan Liou ,  Hsiao-Lin Hsu ,  Yi-Ting Chen ,  Lu-Wei Kuo

IPC: H01L23/544 ,  H01L27/108 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/311

Abstract: A method of forming an overlay mark structure includes the following steps. An insulation layer is formed on a substrate. A first overlay mark is formed in the insulation layer. A metal layer is formed on the substrate. The metal layer covers the insulation layer and the first overlay mark. The metal layer on the first overlay mark is removed. A top surface of the first overlay mark is lower than a top surface of the insulation layer after the step of removing the metal layer on the first overlay mark. A second overlay mark is formed on the metal layer. In the method of forming the overlay mark structure, the first overlay mark may not be covered by the metal layer for avoiding influences on related measurements, and the second overlay mark may be formed on the metal layer for avoiding related defects generated by the height difference.

公开(公告)号：US10395999B1

公开(公告)日：2019-08-27

申请号：US15981053

申请日：2018-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Hao Yang ,  En-Chiuan Liou ,  Hsiao-Lin Hsu ,  Tang-Chun Weng ,  Chia-Ching Lin ,  Yen-Pu Chen

IPC: H01L21/308 ,  H01L27/02 ,  H01L21/66 ,  H01L29/66

Abstract: A method for monitoring fin removal includes providing a substrate having a first region with first fins extending along a first direction and a second region with second fins extending along a second direction, wherein the first direction is perpendicular to the second direction; forming a material layer on the substrate to cover the first fins and the second fins; identically patterning the first fins and the second fins using a first pattern and a second pattern respectively for simultaneously removing parts of the first and second fins, thereby forming first fin features in the first region and second fin features in the second region, wherein the first pattern has a first dimension along the second direction, the second pattern has a second dimension along the second direction, and the second dimension is equal to the first dimension; and monitoring the first fin features using the second fin features.

公开(公告)号：US20190109050A1

公开(公告)日：2019-04-11

申请号：US16200670

申请日：2018-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Lin Hsu ,  En-Chiuan Liou

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having a fin structure extending along a first direction. The fin structure protrudes from a top surface of a trench isolation region and has a first height. A plurality of gate lines including a first gate line and a second gate line extend along a second direction and striding across the fin structure. The first gate line has a discontinuity directly above a gate cut region. The second gate line is disposed in proximity to a dummy fin region, and does not overlap with the dummy fin region. The fin structure has a second height within the dummy fin region, and the second height is smaller than the first height.