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公开(公告)号:US20190361339A1
公开(公告)日:2019-11-28
申请号:US15986799
申请日:2018-05-22
发明人: Yen-Pu Chen , Shu-Yen Liu , Tang-Chun Weng , Tuan-Yen Yu
IPC分类号: G03F1/38
摘要: The present invention provides a photomask, comprising: a substrate, a first region, a second region and a third region are defined thereon, wherein the third region is disposed between the first region and the second region, a patterned layer disposed on the substrate, wherein the patterned layer comprises a first patterned layer disposed in the first region, a second patterned layer disposed in the second region, and a third patterned layer disposed in the third region, and wherein a thickness of the first patterned layer is equal to a thickness of the second patterned layer, the thickness of the first patterned layer is different from a thickness of the third patterned layer, and at least one recess disposed in the third region.
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公开(公告)号:US10395999B1
公开(公告)日:2019-08-27
申请号:US15981053
申请日:2018-05-16
发明人: Cheng-Hao Yang , En-Chiuan Liou , Hsiao-Lin Hsu , Tang-Chun Weng , Chia-Ching Lin , Yen-Pu Chen
IPC分类号: H01L21/308 , H01L27/02 , H01L21/66 , H01L29/66
摘要: A method for monitoring fin removal includes providing a substrate having a first region with first fins extending along a first direction and a second region with second fins extending along a second direction, wherein the first direction is perpendicular to the second direction; forming a material layer on the substrate to cover the first fins and the second fins; identically patterning the first fins and the second fins using a first pattern and a second pattern respectively for simultaneously removing parts of the first and second fins, thereby forming first fin features in the first region and second fin features in the second region, wherein the first pattern has a first dimension along the second direction, the second pattern has a second dimension along the second direction, and the second dimension is equal to the first dimension; and monitoring the first fin features using the second fin features.
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公开(公告)号:US20180047848A1
公开(公告)日:2018-02-15
申请号:US15796874
申请日:2017-10-30
发明人: En-Chiuan Liou , Tang-Chun Weng , Chien-Hao Chen
CPC分类号: H01L29/7851 , H01L29/0653 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要: A semiconductor device and a method of fabricating the same, the semiconductor device includes a plurality of fin shaped structures, a trench, a spacing layer and a dummy gate structure. The fin shaped structures are disposed on a substrate. The trench is disposed between the fin shaped structures. The spacing layer is disposed on sidewalls of the trench, wherein the spacing layer has a top surface lower than a top surface of the fin shaped structures. The dummy gate structure is disposed on the fin shaped structures and across the trench.
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公开(公告)号:US09837540B2
公开(公告)日:2017-12-05
申请号:US14841628
申请日:2015-08-31
发明人: En-Chiuan Liou , Tang-Chun Weng , Chien-Hao Chen
IPC分类号: H01L29/66 , H01L21/762 , H01L29/78 , H01L29/06
CPC分类号: H01L29/7851 , H01L29/0653 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要: A semiconductor device and a method of fabricating the same, the semiconductor device includes a plurality of fin shaped structures, a trench, a spacing layer and a dummy gate structure. The fin shaped structures are disposed on a substrate. The trench is disposed between the fin shaped structures. The spacing layer is disposed on sidewalls of the trench, wherein the spacing layer has a top surface lower than a top surface of the fin shaped structures. The dummy gate structure is disposed on the fin shaped structures and across the trench.
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公开(公告)号:US10747099B2
公开(公告)日:2020-08-18
申请号:US15986799
申请日:2018-05-22
发明人: Yen-Pu Chen , Shu-Yen Liu , Tang-Chun Weng , Tuan-Yen Yu
IPC分类号: G03F1/38 , G03F1/54 , G03F1/50 , H01L21/027
摘要: The present invention provides a photomask, comprising: a substrate, a first region, a second region and a third region are defined thereon, wherein the third region is disposed between the first region and the second region, a patterned layer disposed on the substrate, wherein the patterned layer comprises a first patterned layer disposed in the first region, a second patterned layer disposed in the second region, and a third patterned layer disposed in the third region, and wherein a thickness of the first patterned layer is equal to a thickness of the second patterned layer, the thickness of the first patterned layer is different from a thickness of the third patterned layer, and at least one recess disposed in the third region.
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公开(公告)号:US09837282B1
公开(公告)日:2017-12-05
申请号:US15667641
申请日:2017-08-03
发明人: Tang-Chun Weng , Chia-Ching Lin , Yen-Pu Chen , En-Chiuan Liou
IPC分类号: H01L21/02 , H01L21/308 , H01L21/66 , H01L21/762 , H01L29/66
CPC分类号: H01L22/12 , H01L21/3083 , H01L21/823431 , H01L21/823481 , H01L27/0207 , H01L29/66545 , H01L29/66795
摘要: A semiconductor structure includes a semiconductor substrate with a first region and a second region defined thereon. The first region is disposed adjoining the second region in a first direction. The semiconductor substrate includes fin structures, first recessed fins, and a bump. The fin structures are disposed in the first region. Each fin structure is elongated in the first direction. The first recessed fins are disposed in the second region. Each first recessed fin is elongated in the first direction. A topmost surface of each first recessed fin is lower than a topmost surface of each fin structure. The bump is disposed in the second region and disposed between two adjacent recessed fins in the first direction. A topmost surface of the bump is higher than the topmost surface of each first recessed fin and lower than the topmost surface of each fin structure.
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公开(公告)号:US09761460B1
公开(公告)日:2017-09-12
申请号:US15365967
申请日:2016-12-01
发明人: Tang-Chun Weng , Chia-Ching Lin , Yen-Pu Chen , En-Chiuan Liou
IPC分类号: H01L21/02 , H01L21/308 , H01L29/66 , H01L21/762 , H01L21/66
CPC分类号: H01L22/12 , H01L21/3083 , H01L21/823431 , H01L21/823481 , H01L27/0207 , H01L29/66545 , H01L29/66795
摘要: A method of fabricating a semiconductor structure is provided and includes the following steps. A semiconductor substrate including fin structures is provided. Each fin structure is partly located in a first region and partly located in a second region adjoining the first region. A fin remove process is performed for removing the fin structures in the second region. A fin cut process with a fin cut mask is performed for cutting a part of the fin structures in the first region. The fin cut mask includes cut patterns and a compensation pattern. The cut patterns are located corresponding to a part of the fin structures in the first region. The compensation pattern is located corresponding to the second region of the semiconductor substrate. A fin bump is formed in the second region and corresponding to the compensation pattern after the fin cut process and the fin remove process.
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公开(公告)号:US20170025540A1
公开(公告)日:2017-01-26
申请号:US14841628
申请日:2015-08-31
发明人: En-Chiuan Liou , Tang-Chun Weng , Chien-Hao Chen
CPC分类号: H01L29/7851 , H01L29/0653 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要: A semiconductor device and a method of fabricating the same, the semiconductor device includes a plurality of fin shaped structures, a trench, a spacing layer and a dummy gate structure. The fin shaped structures are disposed on a substrate. The trench is disposed between the fin shaped structures. The spacing layer is disposed on sidewalls of the trench, wherein the spacing layer has a top surface lower than a top surface of the fin shaped structures. The dummy gate structure is disposed on the fin shaped structures and across the trench.
摘要翻译: 半导体器件及其制造方法,半导体器件包括多个鳍状结构,沟槽,间隔层和虚拟栅极结构。 鳍状结构设置在基板上。 沟槽设置在翅片形结构之间。 间隔层设置在沟槽的侧壁上,其中间隔层具有比翅片形结构的顶表面低的顶表面。 虚拟栅极结构设置在鳍状结构上并横跨沟槽。
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公开(公告)号:US20240122078A1
公开(公告)日:2024-04-11
申请号:US18542791
申请日:2023-12-18
发明人: Chia-Chang Hsu , Tang-Chun Weng , Cheng-Yi Lin , Yung-Shen Chen , Chia-Hung Lin
摘要: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.
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公开(公告)号:US11895927B2
公开(公告)日:2024-02-06
申请号:US17319106
申请日:2021-05-13
发明人: Chia-Chang Hsu , Tang-Chun Weng , Cheng-Yi Lin , Yung-Shen Chen , Chia-Hung Lin
摘要: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.
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