公开(公告)号：US20140191285A1

公开(公告)日：2014-07-10

申请号：US14203581

申请日：2014-03-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-I Liao ,  Teng-Chun Hsuan ,  I-Ming Lai ,  Chin-Cheng Chien

IPC: H01L29/165

CPC classification number: H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant. The epitaxial structures and the undoped cap layer include a first semiconductor material having a first lattice constant and a second semiconductor material having a second lattice constant. The second lattice constant is larger than the first lattice constant. The second semiconductor material in the epitaxial structure includes a first concentration and the second semiconductor material in the undoped cap layer includes a second concentration. The second concentration is lower than the first concentration, and is upwardly decreased.

Abstract translation: 具有外延结构的半导体器件包括位于衬底上的栅极结构，在栅极结构的两侧形成在衬底中的外延结构，以及形成在外延结构上的未掺杂的帽层。 外延结构包括掺杂剂。 外延结构和未掺杂的帽层包括具有第一晶格常数的第一半导体材料和具有第二晶格常数的第二半导体材料。 第二晶格常数大于第一晶格常数。 外延结构中的第二半导体材料包括第一浓度，未掺杂帽层中的第二半导体材料包括第二浓度。 第二浓度低于第一浓度，并且向上减少。

公开(公告)号：US20250096000A1

公开(公告)日：2025-03-20

申请号：US18487141

申请日：2023-10-16

Applicant: United Microelectronics Corp.

Inventor： Kun-Ju Li ,  Hsin-Jung Liu ,  Jhih Yuan Chen ,  I-Ming Lai ,  Ang Chan ,  Wei Xin Gao ,  Hsiang Chi Chien ,  Hao-Che Hsu ,  Chau Chung Hou ,  Zong Sian Wu

IPC: H01L21/304 ,  H01L21/306 ,  H01L21/762

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first wafer is provided. The first wafer includes a first substrate and a first device layer. A second wafer is provided. The second wafer includes a second substrate and a second device layer. The second device layer is bonded to the first device layer. An edge trimming process is performed on the first wafer and the second wafer to expose a first upper surface of the first substrate and a second upper surface of the first substrate and to form a damaged region in the first substrate below the first upper surface and the second upper surface. The second upper surface is higher than the first upper surface. A first photoresist layer is formed. The first photoresist layer is located on the second wafer and the second upper surface and exposes the first upper surface and the damaged region. The damaged region is removed by using the first photoresist layer as a mask. The first photoresist layer is removed.