公开(公告)号：US09123744B1

公开(公告)日：2015-09-01

申请号：US14201373

申请日：2014-03-07

申请人： United Microelectronics Corp.

发明人： Chin-I Liao ,  Sheng-Hsu Liu

IPC分类号： H01L29/76 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/16 ,  H01L29/161 ,  H01L29/24

CPC分类号： H01L21/02521 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A method for fabricating a semiconductor device is described. A spacer is formed on a sidewall of a fin structure. A portion of the fin structure is removed to form a cavity exposing at least a portion of the inner sidewall of the spacer. An epitaxy process is performed based on the remaining fin structure to form a semiconductor layer that has a shovel-shaped cross section including: a stem portion in the cavity, and a shovel plane portion contiguous with the stem portion. A semiconductor device is also described, which includes the spacer, the remaining fin structure and the semiconductor layer that are mentioned above.

摘要翻译： 对半导体装置的制造方法进行说明。 间隔件形成在翅片结构的侧壁上。 翼片结构的一部分被去除以形成暴露间隔物的内侧壁的至少一部分的空腔。 基于剩余的翅片结构进行外延工艺以形成具有铲形截面的半导体层，该半导体层包括：腔体中的杆部分和与杆部分相邻的铲平面部分。 还描述了一种半导体器件，其包括上述的间隔物，剩余的鳍结构和半导体层。

公开(公告)号：US20150123210A1

公开(公告)日：2015-05-07

申请号：US14070596

申请日：2013-11-04

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chin-I Liao ,  Chun-Yu Chen

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L29/16 ,  H01L29/66795

摘要： An epitaxial structure for a non-planar transistor is provided. A substrate has a fin-shaped structure. A gate is disposed across the fin-shaped structure. A silicon germanium epitaxial structure is disposed on the fin-shaped structure beside the gate, wherein the silicon germanium epitaxial structure has 4 surfaces and its aspect ratio of width and thickness is at a range of 1:1˜1.3. A method for forming said epitaxial structure is also provided.

摘要翻译： 提供了一种用于非平面晶体管的外延结构。 衬底具有鳍状结构。 门跨越鳍状结构设置。 在栅极旁边的鳍状结构上设置硅锗外延结构，其中硅锗外延结构具有4 <1,1,1“表面，其宽度和厚度的纵横比在1：1〜 1.3。 还提供了一种用于形成所述外延结构的方法。

公开(公告)号：US20150044831A1

公开(公告)日：2015-02-12

申请号：US13962959

申请日：2013-08-09

申请人： UNITED MICROELECTRONICS CORP.

发明人： Yu-Cheng Tung ,  Chin-I Liao

IPC分类号： H01L21/8238

CPC分类号： H01L21/823864 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814

摘要： A semiconductor process includes the following steps. A first gate and a second gate are formed on a substrate. A first stress layer is formed to cover the first gate and the second gate. The first stress layer covering the first gate is etched to form a first spacer beside the first gate, but reserves the first stress layer covering the second gate. A first epitaxial layer is formed beside the first spacer. The first stress layer and the first spacer are entirely removed. A second stress layer is formed to cover the first gate and the second gate. The second stress layer covering the second gate is etched to form a second spacer beside the second gate, but reserves the second stress layer covering the first gate. A second epitaxial layer is formed beside the second spacer. The second stress layer and the second spacer are entirely removed.

摘要翻译： 半导体工艺包括以下步骤。 在基板上形成第一栅极和第二栅极。 形成第一应力层以覆盖第一栅极和第二栅极。 蚀刻覆盖第一栅极的第一应力层以在第一栅极旁边形成第一间隔物，但保留覆盖第二栅极的第一应力层。 在第一间隔物旁边形成第一外延层。 第一应力层和第一间隔件被完全去除。 形成第二应力层以覆盖第一栅极和第二栅极。 蚀刻覆盖第二栅极的第二应力层以在第二栅极旁边形成第二间隔物，但保留覆盖第一栅极的第二应力层。 在第二间隔物旁边形成第二外延层。 完全除去第二应力层和第二间隔物。

公开(公告)号：US20140295634A1

公开(公告)日：2014-10-02

申请号：US14306250

申请日：2014-06-17

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

IPC分类号： H01L29/66

CPC分类号： H01L29/66795 ,  H01L29/1054 ,  H01L29/66484 ,  H01L29/785

摘要： A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from inner to outer. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.

摘要翻译： 多栅极场效应晶体管包括鳍状结构，栅极结构，至少外延结构和梯度盖层。 鳍状结构位于基板上。 栅极结构设置在鳍状结构和衬底的一部分上。 外延结构位于栅极结构旁边的鳍状结构上。 梯度盖层位于每个外延结构上。 梯度盖层是化合物半导体，化合物半导体的成分之一的浓度具有从内向外减小的梯度分布。 此外，本发明还提供一种形成所述多栅极场效应晶体管的多栅极场效应晶体管工艺。

公开(公告)号：US20140235038A1

公开(公告)日：2014-08-21

申请号：US14260294

申请日：2014-04-24

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chin-I Liao ,  Teng-Chun Hsuan ,  Chin-Cheng Chien

IPC分类号： H01L21/02

CPC分类号： H01L29/165 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method for forming epitaxial layer is disclosed. The method includes the steps of providing a semiconductor substrate, and forming an undoped first epitaxial layer in the semiconductor substrate. Preferably, the semiconductor substrate includes at least a recess, the undoped first epitaxial layer has a lattice constant, a bottom thickness, and a side thickness, in which the lattice constant is different from a lattice constant of the semiconductor substrate and the bottom thickness is substantially larger than or equal to the side thickness.

摘要翻译： 公开了一种用于形成外延层的方法。 该方法包括提供半导体衬底以及在半导体衬底中形成未掺杂的第一外延层的步骤。 优选地，半导体衬底至少包括凹部，未掺杂的第一外延层具有晶格常数，底部厚度和侧面厚度，其中晶格常数不同于半导体衬底的晶格常数，底部厚度为 基本上大于或等于侧厚度。

公开(公告)号：US09337193B2

公开(公告)日：2016-05-10

申请号：US14637412

申请日：2015-03-04

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chin-I Liao ,  Chun-Yu Chen

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267

CPC分类号： H01L27/0886 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

摘要： A semiconductor device includes at least two fin-shaped structures, a gate structure, at least two epitaxial structures and a cap. The fin-shaped structures are disposed on a substrate and are covered by the gate structure. The epitaxial structures spaced apart from each other are disposed at one side of the gate structure and respectively directly contact each fin-shaped structure. The cap simultaneously surrounds the epitaxial structures, and at least two adjacent caps are merged together.

摘要翻译： 半导体器件包括至少两个鳍状结构，栅极结构，至少两个外延结构和帽。 鳍状结构设置在基板上并被栅极结构覆盖。 彼此间隔开的外延结构设置在栅极结构的一侧，并且分别直接接触每个鳍状结构。 盖同时围绕外延结构，并且至少两个相邻的盖合并在一起。

公开(公告)号：US09112030B2

公开(公告)日：2015-08-18

申请号：US14070596

申请日：2013-11-04

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chin-I Liao ,  Chun-Yu Chen

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/16

CPC分类号： H01L29/785 ,  H01L29/16 ,  H01L29/66795

摘要： An epitaxial structure for a non-planar transistor is provided. A substrate has a fin-shaped structure. A gate is disposed across the fin-shaped structure. A silicon germanium epitaxial structure is disposed on the fin-shaped structure beside the gate, wherein the silicon germanium epitaxial structure has 4 surfaces and its aspect ratio of width and thickness is at a range of 1:1˜1.3. A method for forming said epitaxial structure is also provided.

摘要翻译： 提供了一种用于非平面晶体管的外延结构。 衬底具有鳍状结构。 门跨越鳍状结构设置。 在栅极旁边的鳍状结构上设置硅锗外延结构，其中硅锗外延结构具有4 <1,1,1“表面，其宽度和厚度的纵横比在1：1〜 1.3。 还提供了一种用于形成所述外延结构的方法。

公开(公告)号：US20150179645A1

公开(公告)日：2015-06-25

申请号：US14637412

申请日：2015-03-04

申请人： United Microelectronics Corp.

发明人： Chin-I Liao ,  Chun-Yu Chen

IPC分类号： H01L27/088 ,  H01L29/267 ,  H01L29/165 ,  H01L29/78 ,  H01L29/16 ,  H01L29/161

CPC分类号： H01L27/0886 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

摘要： A semiconductor device includes at least two fin-shaped structures, a gate structure, at least two epitaxial structures and a cap. The fin-shaped structures are disposed on a substrate and are covered by the gate structure. The epitaxial structures spaced apart from each other are disposed at one side of the gate structure and respectively directly contact each fin-shaped structure. The cap simultaneously surrounds the epitaxial structures, and at least two adjacent caps are merged together.

摘要翻译： 半导体器件包括至少两个鳍状结构，栅极结构，至少两个外延结构和帽。 鳍状结构设置在基板上并被栅极结构覆盖。 彼此间隔开的外延结构设置在栅极结构的一侧，并且分别直接接触每个鳍状结构。 盖同时围绕外延结构，并且至少两个相邻的盖合并在一起。

公开(公告)号：US09064893B2

公开(公告)日：2015-06-23

申请号：US13892424

申请日：2013-05-13

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chin-I Liao ,  Chin-Cheng Chien

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L29/66636 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/66795

摘要： A manufacturing method of a semiconductor device is provided. The method includes at least the following steps. A gate structure is formed on a substrate. An epitaxial structure is formed on the substrate, wherein the epitaxial structure comprises SiGe, and the Ge concentration in the epitaxial structure is equal to or higher than 45%. A first cap layer is formed on the epitaxial structure, wherein the first cap layer comprises Si. The first cap layer is doped with boron for forming a flat top surface of the first cap layer.

摘要翻译： 提供一种半导体器件的制造方法。 该方法至少包括以下步骤。 在基板上形成栅极结构。 在衬底上形成外延结构，其中外延结构包括SiGe，外延结构中的Ge浓度等于或高于45％。 第一盖层形成在外延结构上，其中第一盖层包括Si。 第一盖层掺杂有硼以形成第一盖层的平坦顶表面。

公开(公告)号：US20150145067A1

公开(公告)日：2015-05-28

申请号：US14092942

申请日：2013-11-28

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chin-I Liao ,  Chun-Yu Chen

IPC分类号： H01L29/78

CPC分类号： H01L29/7851 ,  H01L29/7848

摘要： A fin structure includes a substrate and a fin disposed on a top surface of the substrate. The fin has a height. An epitaxial structure surrounds the fin and the epitaxial structure has a top point which is the farthest point on the epitaxial structure away from the top surface of the substrate. There is a distance between the top point and the top surface of the substrate. A rational number of the distance to the height is not less than 7.

摘要翻译： 翅片结构包括设置在基板的顶表面上的基板和翅片。 翅片有一个高度。 外延结构围绕鳍状物并且外延结构具有顶点，该顶点是离开衬底顶表面的外延结构上的最远点。 在基板的顶点和顶面之间存在距离。 到高度的距离的合理数量不小于7。