公开(公告)号：US09653346B2

公开(公告)日：2017-05-16

申请号：US14800697

申请日：2015-07-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Chin Lin ,  Kuei-Chun Hung ,  Jerry Che Jen Hu ,  Ming-Jui Chen ,  Chen-Hsien Hsu

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535

CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/7851

Abstract: An integrated circuits structure includes a semiconductor substrate, at least an non-planar field effect transistor (FET) device formed on the semiconductor substrate, and an interconnection structure formed on the semiconductor substrate. The non-planar FET device includes a plurality of fins and a gate electrode. The interconnection structure includes a plurality of first group metals and a plurality of second group metals. The first group metals are formed on the non-planar FET and the second group metals are formed on the first group metals. The first group metals include a first metal pitch and the second group metals include a second metal pitch. The second metal pitch is 1.2-1.5 times to the first metal pitch.

公开(公告)号：US09905562B2

公开(公告)日：2018-02-27

申请号：US15484126

申请日：2017-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Chin Lin ,  Kuei-Chun Hung ,  Jerry Che Jen Hu ,  Ming-Jui Chen ,  Chen-Hsien Hsu

IPC: H01L27/118 ,  H01L27/092 ,  H01L27/02 ,  H01L29/06 ,  H01L27/088 ,  H01L23/522 ,  H01L23/528 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/49

CPC classification number: H01L27/0924 ,  H01L21/28518 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4983 ,  H01L29/785 ,  H01L2224/48132 ,  H01L2924/00014 ,  H01L2924/37001 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor IC layout structure includes a plurality of first active regions arranged along a second direction, a plurality of second active regions arranged along the second direction, a plurality of gate structures extending along a first direction and respectively straddling the first active regions and the second active regions, a plurality of first conductive structures extending along the first direction, and a plurality of second conductive structures formed on the gate structures. The second active regions are isolated from the first active regions. The first direction is perpendicular to the second direction. The first conductive structures are formed on the first active regions and the second active regions. The second conductive structures include a plurality of slot-type second conductive structures extended along the second direction and a plurality of island-type second conductive structures formed on the gate structures.

公开(公告)号：US09673145B2

公开(公告)日：2017-06-06

申请号：US14859367

申请日：2015-09-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Chin Lin ,  Kuei-Chun Hung ,  Jerry Che Jen Hu ,  Ming-Jui Chen ,  Chen-Hsien Hsu

IPC: H01L29/82 ,  H01L23/528 ,  H01L29/78 ,  H01L29/06 ,  H01L23/522 ,  H01L23/00 ,  H01L27/02 ,  H01L27/118

CPC classification number: H01L27/0924 ,  H01L21/28518 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4983 ,  H01L29/785 ,  H01L2224/48132 ,  H01L2924/00014 ,  H01L2924/37001 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor integrated circuit layout structure includes a first active region, a second active region isolating from the first active region, a gate structure straddling the first active region and the second active region, and a plurality of conductive structures. The first active region at two opposite sides of the gate structure respectively forms a first source region and a first drain region. The second active region at two opposite sides of the gate structure respectively forms a second source region and a second drain region. The conductive structures include a plurality of slot-type conductive structures and one island-type conductive structure. The slot-type conductive structures are respectively formed on the first source region, the first drain region, the second source region and the second drain region. The island-type conductive structure is formed on the gate structure.