公开(公告)号：US20250142895A1

公开(公告)日：2025-05-01

申请号：US18523894

申请日：2023-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pei-Lun Jheng ,  Po-Jui Chiang ,  Chao-Sheng Cheng ,  Ming-Jen Chang ,  Ko-Chin Chang ,  Yu-Ming Liu

IPC: H01L29/423 ,  H01L29/66 ,  H10B41/30

Abstract: An embedded flash memory structure, including a semiconductor substrate, an erase gate on the semiconductor substrate, two floating gates respectively at two sides of the erase gate on the semiconductor substrate, two word lines respectively at outer sides of the two floating gates, and two metal control gates respectively on the two floating gates, wherein a sacrificial layer is at at least one side of the metal control gate, and the sacrificial layer is between the metal control gate and the erase gate or between the metal control gate and the word line.

公开(公告)号：US20250031365A1

公开(公告)日：2025-01-23

申请号：US18365245

申请日：2023-08-04

Applicant: United Microelectronics Corp.

Inventor： Hsin-Chieh Lin ,  Po-Jui Chiang ,  Pei Lun Jheng ,  Chao-Sheng Cheng ,  Ming-Jen Chang ,  Ko Chin Chang ,  Yu Ming Liu

IPC: H10B41/30 ,  H01L21/28 ,  H01L29/423

Abstract: A memory structure including a substrate, charge storage layers, and a gate is provided. The charge storage layers are located on the substrate. The gate is located on the substrate on one side of the charge storage layers. The gate extends along a first direction. The gate has a protruding portion protruding along a second direction. The second direction intersects the first direction. The protruding portion is located between two adjacent charge storage layers arranged along the first direction.