公开(公告)号：US11366604B1

公开(公告)日：2022-06-21

申请号：US17210545

申请日：2021-03-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Chin Chang ,  Ming-Jen Chang ,  Cheng-Hsiao Lai ,  Yu-Syuan Lin ,  Chi-Fa Lien ,  Ying-Ting Lin ,  Yung-Tsai Hsu

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/28 ,  G11C16/22

Abstract: A physically unclonable function includes a flash memory, a current comparator and a controller. The flash memory includes a plurality of memory cells. A method of operating the physically unclonable function circuit includes the controller setting the plurality of memory cells to an initial data state, the controller setting the plurality of memory cells between the initial data state and an adjacent data state of the initial data state, the current comparator reading a first current from a memory cell in a first section of the plurality of the memory cells, the current comparator reading a second current from a memory cell in a second section of the plurality of the memory cells, and the current comparator outputting a random bit according to the first current and the second current.

公开(公告)号：US20250031365A1

公开(公告)日：2025-01-23

申请号：US18365245

申请日：2023-08-04

Applicant: United Microelectronics Corp.

Inventor： Hsin-Chieh Lin ,  Po-Jui Chiang ,  Pei Lun Jheng ,  Chao-Sheng Cheng ,  Ming-Jen Chang ,  Ko Chin Chang ,  Yu Ming Liu

IPC: H10B41/30 ,  H01L21/28 ,  H01L29/423

Abstract: A memory structure including a substrate, charge storage layers, and a gate is provided. The charge storage layers are located on the substrate. The gate is located on the substrate on one side of the charge storage layers. The gate extends along a first direction. The gate has a protruding portion protruding along a second direction. The second direction intersects the first direction. The protruding portion is located between two adjacent charge storage layers arranged along the first direction.

公开(公告)号：US11823746B2

公开(公告)日：2023-11-21

申请号：US17673829

申请日：2022-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shan Ho ,  Ying-Ting Lin ,  Chung-Yi Luo ,  Kuo-Cheng Chou ,  Cheng-Hsiao Lai ,  Ming-Jen Chang ,  Yung-Tsai Hsu ,  Cheng-Chieh Cheng

IPC: G11C16/28 ,  G11C16/24 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/28 ,  G11C16/08 ,  G11C16/102 ,  G11C16/24

Abstract: A memory sector with trimmed reference currents, including eight unit cells corresponding to an even word line and eight unit cells corresponding to an odd word line, and each unit cell has erased state and programmed state, wherein the logic state of unit cell corresponding to the odd word line is determined by a first reference current based on cell currents of the 8 unit cells corresponding to the even word line in programmed state and cell currents of the eight unit cells corresponding to the odd word line in erased state, and the logic state of unit cell corresponding to the even word line is determined by a second reference current based on cell currents of the eight unit cells corresponding to the even word line in erased state and cell currents of the 8 unit cells corresponding to the odd word line in programmed state.

公开(公告)号：US20230223091A1

公开(公告)日：2023-07-13

申请号：US17673829

申请日：2022-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shan Ho ,  Ying-Ting Lin ,  Chung-Yi Luo ,  Kuo-Cheng Chou ,  Cheng-Hsiao Lai ,  Ming-Jen Chang ,  Yung-Tsai Hsu ,  Cheng-Chieh Cheng

IPC: G11C16/28 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24

CPC classification number: G11C16/28 ,  G11C16/102 ,  G11C16/08 ,  G11C16/24

Abstract: A memory sector with trimmed reference currents, including eight unit cells corresponding to an even word line and eight unit cells corresponding to an odd word line, and each unit cell has erased state and programmed state, wherein the logic state of unit cell corresponding to the odd word line is determined by a first reference current based on cell currents of the 8 unit cells corresponding to the even word line in programmed state and cell currents of the eight unit cells corresponding to the odd word line in erased state, and the logic state of unit cell corresponding to the even word line is determined by a second reference current based on cell currents of the eight unit cells corresponding to the even word line in erased state and cell currents of the 8 unit cells corresponding to the odd word line in programmed state.