中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

23 records (took 0.017 seconds)

    MEMORY CELL AND FABRICATING METHOD OF THE SAME
    1.
    发明申请
    MEMORY CELL AND FABRICATING METHOD OF THE SAME 有权

    公开(公告)号：US20220336606A1

    公开(公告)日：2022-10-20

    申请号：US17853954

    申请日：2022-06-30

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Hao Pan ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Szu-Ping Wang ,  Po-Hsuan Chen ,  Chao-Sheng Cheng

    IPC: H01L29/423 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66

    Abstract: A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.

    SEMICONDUCTOR INTEGRATED DEVICE INCLUDING CAPACITOR AND MEMORY CELL AND METHOD OF FORMING THE SAME
    2.
    发明申请
    SEMICONDUCTOR INTEGRATED DEVICE INCLUDING CAPACITOR AND MEMORY CELL AND METHOD OF FORMING THE SAME 有权
    包括电容器和存储单元的半导体集成器件及其形成方法

    公开(公告)号：US20170025429A1

    公开(公告)日：2017-01-26

    申请号：US14805484

    申请日：2015-07-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Han Jen ,  Chao-Sheng Cheng

    IPC: H01L27/115 ,  H01L49/02 ,  H01L29/788 ,  H01L29/06 ,  H01L29/66 ,  H01L27/07 ,  H01L29/423

    CPC classification number: H01L29/66825 ,  H01L27/0629 ,  H01L27/11524 ,  H01L28/60 ,  H01L28/87 ,  H01L28/91

    Abstract: A semiconductor integrated device and a method of forming the same, the semiconductor integrated device includes a substrate, at least one shallow trench isolation, a memory cell device and a poly-insulator-poly capacitor. A capacitor region and a memory cell region are defined on the substrate. The at least one shallow trench isolation is formed in the substrate. The memory cell device is disposed on the at least one shallow trench isolation in the memory cell region and includes a double polysilicon gate. The poly-insulator-poly capacitor is disposed on the at least one shallow trench isolation in the capacitor region, wherein the poly-insulator-poly capacitor directly contacts the at least one shallow trench isolation.

    Abstract translation: 半导体集成器件及其形成方法，半导体集成器件包括衬底，至少一个浅沟槽隔离，存储单元器件和多绝缘体 - 多晶硅电容器。 在基板上限定电容器区域和存储单元区域。 在衬底中形成至少一个浅沟槽隔离。 存储单元装置设置在存储单元区域中的至少一个浅沟槽隔离层上并且包括双多晶硅栅极。 多绝缘体 - 多晶硅电容器设置在电容器区域中的至少一个浅沟槽隔离上，其中多绝缘体 - 多晶硅电容器直接接触至少一个浅沟槽隔离。

    MANUFACTURING METHOD OF GATE STRUCTURE
    3.
    发明公开
    MANUFACTURING METHOD OF GATE STRUCTURE 审中-公开

    公开(公告)号：US20240063052A1

    公开(公告)日：2024-02-22

    申请号：US17949186

    申请日：2022-09-20

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tzu-Feng Weng ,  Chao-Sheng Cheng ,  Chi-Cheng Huang

    IPC: H01L21/762 ,  H01L21/28 ,  H01L29/66

    CPC classification number: H01L21/76264 ,  H01L21/28141 ,  H01L29/66545

    Abstract: A manufacturing method of a gate structure includes the following steps. A semiconductor substrate is provided. An isolation structure is formed in the semiconductor substrate and surrounds an active region in the semiconductor substrate. A gate pattern is formed on the active region and the isolation structure. The gate pattern includes a first gate structure and a first capping layer disposed on the first gate structure. A part of the first capping layer located above an interface between the active region and the isolation structure is removed for exposing a part of the first gate structure located above the interface between the active region and the isolation structure. A removing process is performed for reducing a thickness of the part of the first gate structure located above the interface between the active region and the isolation structure.

    MANUFACTURING METHOD OF INTEGRATED CIRCUIT
    5.
    发明申请
    MANUFACTURING METHOD OF INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20190051530A1

    公开(公告)日：2019-02-14

    申请号：US15675811

    申请日：2017-08-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chao-Sheng Cheng

    IPC: H01L21/28 ,  H01L21/311 ,  H01L21/8234

    Abstract: A manufacturing method of an integrated circuit includes following steps. A dummy gate with a first mask structure formed thereon and a semiconductor gate with a second mask structure formed thereon are formed on a substrate. A top surface of the semiconductor gate is lower than a top surface of the dummy gate. A first removing process is performed to remove the first mask structure and a part of the second mask structure. A dielectric layer is formed covering the dummy gate, the semiconductor gate, and the second mask structure. A second removing process is performed to remove the dielectric layer above the dummy gate. The dummy gate is removed for forming a trench. A metal gate structure is formed in the trench. The semiconductor gate is covered by the second mask structure during the second removing process and the step of removing the dummy gate.

    Semiconductor integrated device including capacitor and memory cell and method of forming the same
    8.
    发明授权
    Semiconductor integrated device including capacitor and memory cell and method of forming the same 有权
    包括电容器和存储单元的半导体集成器件及其形成方法

    公开(公告)号：US09570456B1

    公开(公告)日：2017-02-14

    申请号：US14805484

    申请日：2015-07-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Han Jen ,  Chao-Sheng Cheng

    IPC: H01L27/07 ,  H01L27/115 ,  H01L49/02 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/788

    CPC classification number: H01L29/66825 ,  H01L27/0629 ,  H01L27/11524 ,  H01L28/60 ,  H01L28/87 ,  H01L28/91

    Abstract: A semiconductor integrated device and a method of forming the same, the semiconductor integrated device includes a substrate, at least one shallow trench isolation, a memory cell device and a poly-insulator-poly capacitor. A capacitor region and a memory cell region are defined on the substrate. The at least one shallow trench isolation is formed in the substrate. The memory cell device is disposed on the at least one shallow trench isolation in the memory cell region and includes a double polysilicon gate. The poly-insulator-poly capacitor is disposed on the at least one shallow trench isolation in the capacitor region, wherein the poly-insulator-poly capacitor directly contacts the at least one shallow trench isolation.

    Abstract translation: 半导体集成器件及其形成方法，半导体集成器件包括衬底，至少一个浅沟槽隔离，存储单元器件和多绝缘体 - 多晶硅电容器。 在基板上限定电容器区域和存储单元区域。 在衬底中形成至少一个浅沟槽隔离。 存储单元装置设置在存储单元区域中的至少一个浅沟槽隔离层上并且包括双多晶硅栅极。 多绝缘体 - 多晶硅电容器设置在电容器区域中的至少一个浅沟槽隔离上，其中多绝缘体 - 多晶硅电容器直接接触至少一个浅沟槽隔离。

Patent Agency Ranking