公开(公告)号：US20250126889A1

公开(公告)日：2025-04-17

申请号：US18505094

申请日：2023-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： YUERAN QIAO ,  Yi Liu ,  Guohai Zhang ,  Genmao Liu ,  Lei Zhu

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/78

Abstract: The invention provides a semiconductor structure comprising a silicon-on-insulator (SOI) substrate, which comprises a silicon layer and an insulating layer stacked from bottom to top, a phosphosilicate glass (PGS) on the insulating layer, and a fluorosilicate glass (FSG) on the phosphosilicate glass. The probability of ions infiltrating into the transistor can be reduced and the yield of products can be improved.

公开(公告)号：US12094758B2

公开(公告)日：2024-09-17

申请号：US17843089

申请日：2022-06-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Tsai Hung ,  Yi Liu ,  Guo-Hai Zhang ,  Ching-Hwa Tey

IPC: H01L21/762 ,  H01L23/00 ,  H01L27/12

CPC classification number: H01L21/76251 ,  H01L23/562 ,  H01L23/564 ,  H01L27/1203

Abstract: A semiconductor structure is provided. The semiconductor structure includes a wafer structure. The wafer structure has a normal region and a trimmed region adjacent to the normal region. A top surface of the trimmed region is lower than a top surface of the normal region. The semiconductor structure includes a dielectric layer and a conductive layer disposed on the wafer structure in the normal region and the trimmed region. The semiconductor structure includes a protective layer disposed on a portion of the dielectric layer in the trimmed region and a portion of the conductive layer in the trimmed region. The semiconductor structure includes another dielectric layer disposed on a portion of the dielectric layer in the normal region and a portion of the conductive layer in the normal region and on the protective layer.

公开(公告)号：US11201134B2

公开(公告)日：2021-12-14

申请号：US16853714

申请日：2020-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yonghui Gao ,  Yi Liu ,  Guohai Zhang

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/3105

Abstract: A method of manufacturing a semiconductor device includes the following steps. A device wafer having a product-obtaining part and an edge part surrounding the product-obtaining part is provided. A passivation layer is formed to cover the device wafer. A first oxide cap layer is formed to cover the passivation layer. An edge trimming process is performed to polish an edge part of the first oxide cap layer, an edge part of the passivation layer and the edge part of the device wafer. A removing process is performed to remove the first oxide cap layer after the edge trimming process is performed. A second oxide cap layer is formed to cover the first oxide cap layer and the edge part of the device wafer.