公开(公告)号：US12040370B2

公开(公告)日：2024-07-16

申请号：US17376151

申请日：2021-07-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Cheng Hung ,  Yu-Jen Liu

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/42372 ,  H01L21/823437 ,  H01L29/78

Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a gate structure which extends along a first direction, and a plurality of supporting patterns which are separated from each other and arranged along a second direction which is perpendicular to the first direction.

公开(公告)号：US11227769B2

公开(公告)日：2022-01-18

申请号：US16833685

申请日：2020-03-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Jung Tang ,  Yu-Jen Liu

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/49

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming an interlayer dielectric (ILD) layer around the gate structure; performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate; forming an inter-metal dielectric (IMD) layer on the metal gate; forming a metal interconnection in the IMD layer; and performing a high pressure anneal (HPA) process for improving work function variation of the metal gate.

公开(公告)号：US09847392B1

公开(公告)日：2017-12-19

申请号：US15291058

申请日：2016-10-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ping Huang ,  Yu-Jen Liu ,  Hsin-Kai Chiang

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/16 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7843

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure on the substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a gate structure on the fin-shaped structure and the STI and the fin-shaped structure directly under the gate structure includes a first epitaxial layer; forming a source region having first conductive type adjacent to one side of the gate structure; and forming a first drain region having a second conductive type adjacent to another side of the gate structure.

公开(公告)号：US11417532B2

公开(公告)日：2022-08-16

申请号：US17159183

申请日：2021-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Kang Lien ,  Wei-Cheng Hung ,  Yu-Jen Liu

IPC: H01L21/308 ,  G06F30/392 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238

Abstract: The invention provides a method for reducing mismatch of semiconductor device patterns, which comprises the following steps: defining an initial lithography area which partially overlaps a target gate structure, a first gate structure and a second gate structure; if a length and a width of the target gate structure are smaller than a preset channel length and a preset channel width respectively, adjusting and reducing the area of the initial lithography area to define a second lithography area. The second lithography area partially overlaps with the target gate structure but does not overlap with the first gate structure and the second gate structure, and the second lithography region is defined as the active area.

公开(公告)号：US20210272813A1

公开(公告)日：2021-09-02

申请号：US16833685

申请日：2020-03-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Jung Tang ,  Yu-Jen Liu

IPC: H01L21/28 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming an interlayer dielectric (ILD) layer around the gate structure; performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate; forming an inter-metal dielectric (IMD) layer on the metal gate; forming a metal interconnection in the IMD layer; and performing a high pressure anneal (HPA) process for improving work function variation of the metal gate.

公开(公告)号：US20240222457A1

公开(公告)日：2024-07-04

申请号：US18608949

申请日：2024-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Cheng Hung ,  Yu-Jen Liu

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/42372 ,  H01L21/823437 ,  H01L29/78

Abstract: Abstract of Disclosure The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a transistor disposed on the substrate, wherein the transistor comprises a gate structure, a source and a drain, and the gate structure of the transistor located on the substrate and extending along a first direction, and a plurality of supporting patterns located in the gate structure of the transistor, wherein the plurality of supporting patterns are separated from each other and arranged along a second direction, wherein the second direction is perpendicular to the first direction, and wherein at least four supporting patterns of the plurality of supporting patterns constitute a supporting pattern dashed line, wherein the supporting pattern dashed line extends along the second direction.

公开(公告)号：US20220406912A1

公开(公告)日：2022-12-22

申请号：US17376151

申请日：2021-07-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Cheng Hung ,  Yu-Jen Liu

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/8234

Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a gate structure which extends along a first direction, and a plurality of supporting patterns which are separated from each other and arranged along a second direction which is perpendicular to the first direction.

公开(公告)号：US20220199408A1

公开(公告)日：2022-06-23

申请号：US17159183

申请日：2021-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Kang Lien ,  Wei-Cheng Hung ,  Yu-Jen Liu

IPC: H01L21/308 ,  G06F30/392

Abstract: The invention provides a method for reducing mismatch of semiconductor device patterns, which comprises the following steps: defining an initial lithography area which partially overlaps a target gate structure, a first gate structure and a second gate structure; if a length and a width of the target gate structure are smaller than a preset channel length and a preset channel width respectively, adjusting and reducing the area of the initial lithography area to define a second lithography area. The second lithography area partially overlaps with the target gate structure but does not overlap with the first gate structure and the second gate structure, and the second lithography region is defined as the active area.